move DivPipe(?!Core).* classes to div_pipe.py

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index 4e613f0d60f4bc1eb27a40a4ca23dd0d244fb237..75a1b5c87c649cdbd25fe4f19df71dafea7e7ff7 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -74,32 +74,6 @@ class DivPipeCoreOperation(enum.IntEnum):
                       **kwargs)
 
 
-# TODO: move to suitable location
-class DivPipeBaseData:
-    """ input data base type for ``DivPipe``.
-    """
-
-    def __init__(self, pspec):
-        """ Create a ``DivPipeBaseData`` instance. """
-        width = pspec['width']
-        self.out_do_z = Signal(reset_less=True)
-        self.oz = Signal(width, reset_less=True)
-
-        self.ctx = FPPipeContext(pspec)  # context: muxid, operator etc.
-        self.muxid = self.ctx.muxid             # annoying. complicated.
-
-    def __iter__(self):
-        """ Get member signals. """
-        yield self.out_do_z
-        yield self.oz
-        yield from self.ctx
-
-    def eq(self, rhs):
-        """ Assign member signals. """
-        return [self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
-                self.ctx.eq(i.ctx)]
-
-
 class DivPipeCoreInputData:
     """ input data type for ``DivPipeCore``.
 
@@ -142,33 +116,6 @@ class DivPipeCoreInputData:
                 self.operation.eq(rhs.operation)]  # FIXME: delete.
 
 
-# TODO: move to suitable location
-class DivPipeInputData(DivPipeCoreInputData, DivPipeBaseData):
-    """ input data type for ``DivPipe``.
-    """
-
-    def __init__(self, core_config):
-        """ Create a ``DivPipeInputData`` instance. """
-        DivPipeCoreInputData.__init__(self, core_config)
-        DivPipeBaseData.__init__(self, pspec) # XXX TODO args
-        self.out_do_z = Signal(reset_less=True)
-        self.oz = Signal(width, reset_less=True)
-
-        self.ctx = FPPipeContext(pspec)  # context: muxid, operator etc.
-        self.muxid = self.ctx.muxid             # annoying. complicated.
-
-    def __iter__(self):
-        """ Get member signals. """
-        yield from DivPipeCoreInputData.__iter__(self)
-        yield from DivPipeBaseData.__iter__(self)
-
-    def eq(self, rhs):
-        """ Assign member signals. """
-        return DivPipeBaseData.eq(self, rhs) + \
-               DivPipeCoreInputData.eq(self, rhs)
-
-
-
 class DivPipeCoreInterstageData:
     """ interstage data type for ``DivPipeCore``.
 
@@ -225,30 +172,6 @@ class DivPipeCoreInterstageData:
                 self.compare_rhs.eq(rhs.compare_rhs)]
 
 
-# TODO: move to suitable location
-class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
-    """ interstage data type for ``DivPipe``.
-
-    :attribute core_config: ``DivPipeCoreConfig`` instance describing the
-        configuration to be used.
-    """
-
-    def __init__(self, core_config):
-        """ Create a ``DivPipeCoreInterstageData`` instance. """
-        DivPipeCoreInterstageData.__init__(self, core_config)
-        DivPipeBaseData.__init__(self, pspec) # XXX TODO args
-
-    def __iter__(self):
-        """ Get member signals. """
-        yield from DivPipeInterstageData.__iter__(self)
-        yield from DivPipeBaseData.__iter__(self)
-
-    def eq(self, rhs):
-        """ Assign member signals. """
-        return DivPipeBaseData.eq(self, rhs) + \
-               DivPipeCoreInterstageData.eq(self, rhs)
-
-
 class DivPipeCoreOutputData:
     """ output data type for ``DivPipeCore``.
 
@@ -280,39 +203,6 @@ class DivPipeCoreOutputData:
                 self.remainder.eq(rhs.remainder)]
 
 
-# TODO: move to suitable location
-class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData):
-    """ interstage data type for ``DivPipe``.
-
-    :attribute core_config: ``DivPipeCoreConfig`` instance describing the
-        configuration to be used.
-    """
-
-    def __init__(self, core_config):
-        """ Create a ``DivPipeCoreOutputData`` instance. """
-        DivPipeCoreOutputData.__init__(self, core_config)
-        DivPipeBaseData.__init__(self, pspec) # XXX TODO args
-
-    def __iter__(self):
-        """ Get member signals. """
-        yield from DivPipeOutputData.__iter__(self)
-        yield from DivPipeBaseData.__iter__(self)
-
-    def eq(self, rhs):
-        """ Assign member signals. """
-        return DivPipeBaseData.eq(self, rhs) + \
-               DivPipeCoreOutputData.eq(self, rhs)
-
-
-class DivPipeBaseStage:
-    """ Base Mix-in for DivPipe*Stage """
-
-    def _elaborate(self, m, platform):
-        m.d.comb += self.o.oz.eq(self.i.oz)
-        m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
-        m.d.comb += self.o.ctx.eq(self.i.ctx)
-
-
 class DivPipeCoreSetupStage(Elaboratable):
     """ Setup Stage of the core of the div/rem/sqrt/rsqrt pipeline. """
 
@@ -482,7 +372,6 @@ class DivPipeCoreCalculateStage(Elaboratable):
         DivPipeBaseStage._elaborate(self, m, platform)
 
 
-
 class DivPipeCoreFinalStage(Elaboratable):
     """ Final Stage of the core of the div/rem/sqrt/rsqrt pipeline. """
 
@@ -521,4 +410,3 @@ class DivPipeCoreFinalStage(Elaboratable):
 
         # XXX in DivPipeFinalStage
         DivPipeBaseStage._elaborate(self, m, platform)
-

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
new file mode 100644 (file)
index 0000000..02de78e
--- /dev/null
+++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: LGPL-2.1-or-later
+# See Notices.txt for copyright information
+""" div/rem/sqrt/rsqrt pipeline. """
+from .core import (DivPipeCoreConfig, DivPipeCoreInputData,
+                   DivPipeCoreInterstageData, DivPipeCoreOutputData)
+
+
+class DivPipeBaseData:
+    """ input data base type for ``DivPipe``.
+    """
+
+    def __init__(self, pspec):
+        """ Create a ``DivPipeBaseData`` instance. """
+        width = pspec['width']
+        self.out_do_z = Signal(reset_less=True)
+        self.oz = Signal(width, reset_less=True)
+
+        self.ctx = FPPipeContext(pspec)  # context: muxid, operator etc.
+        self.muxid = self.ctx.muxid             # annoying. complicated.
+
+    def __iter__(self):
+        """ Get member signals. """
+        yield self.out_do_z
+        yield self.oz
+        yield from self.ctx
+
+    def eq(self, rhs):
+        """ Assign member signals. """
+        return [self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+                self.ctx.eq(i.ctx)]
+
+
+class DivPipeInputData(DivPipeCoreInputData, DivPipeBaseData):
+    """ input data type for ``DivPipe``.
+    """
+
+    def __init__(self, core_config):
+        """ Create a ``DivPipeInputData`` instance. """
+        DivPipeCoreInputData.__init__(self, core_config)
+        DivPipeBaseData.__init__(self, pspec)  # XXX TODO args
+        self.out_do_z = Signal(reset_less=True)
+        self.oz = Signal(width, reset_less=True)
+
+        self.ctx = FPPipeContext(pspec)  # context: muxid, operator etc.
+        self.muxid = self.ctx.muxid             # annoying. complicated.
+
+    def __iter__(self):
+        """ Get member signals. """
+        yield from DivPipeCoreInputData.__iter__(self)
+        yield from DivPipeBaseData.__iter__(self)
+
+    def eq(self, rhs):
+        """ Assign member signals. """
+        return DivPipeBaseData.eq(self, rhs) + \
+            DivPipeCoreInputData.eq(self, rhs)
+
+
+class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
+    """ interstage data type for ``DivPipe``.
+
+    :attribute core_config: ``DivPipeCoreConfig`` instance describing the
+        configuration to be used.
+    """
+
+    def __init__(self, core_config):
+        """ Create a ``DivPipeCoreInterstageData`` instance. """
+        DivPipeCoreInterstageData.__init__(self, core_config)
+        DivPipeBaseData.__init__(self, pspec)  # XXX TODO args
+
+    def __iter__(self):
+        """ Get member signals. """
+        yield from DivPipeInterstageData.__iter__(self)
+        yield from DivPipeBaseData.__iter__(self)
+
+    def eq(self, rhs):
+        """ Assign member signals. """
+        return DivPipeBaseData.eq(self, rhs) + \
+            DivPipeCoreInterstageData.eq(self, rhs)
+
+
+class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData):
+    """ interstage data type for ``DivPipe``.
+
+    :attribute core_config: ``DivPipeCoreConfig`` instance describing the
+        configuration to be used.
+    """
+
+    def __init__(self, core_config):
+        """ Create a ``DivPipeCoreOutputData`` instance. """
+        DivPipeCoreOutputData.__init__(self, core_config)
+        DivPipeBaseData.__init__(self, pspec)  # XXX TODO args
+
+    def __iter__(self):
+        """ Get member signals. """
+        yield from DivPipeOutputData.__iter__(self)
+        yield from DivPipeBaseData.__iter__(self)
+
+    def eq(self, rhs):
+        """ Assign member signals. """
+        return DivPipeBaseData.eq(self, rhs) + \
+            DivPipeCoreOutputData.eq(self, rhs)
+
+
+class DivPipeBaseStage:
+    """ Base Mix-in for DivPipe*Stage """
+
+    def _elaborate(self, m, platform):
+        m.d.comb += self.o.oz.eq(self.i.oz)
+        m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
+        m.d.comb += self.o.ctx.eq(self.i.ctx)