Revert "Greatly speed up test_pipe_caller.py"

This reverts commit 54025cace312817b0f9d831865441a0e52db573a.

diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index e36a3f546037b29abc753fc6e988eba10c0276df..55ce27d4576614c341e4f82d816ffbdf0f8a17d3 100644 (file)
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -61,18 +61,10 @@ def set_extra_alu_inputs(alu, dec2, sim):
     yield alu.p.data_i.carry_in.eq(carry)
     so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
     yield alu.p.data_i.so.eq(so)
-
-def cleanup_conditions(conditions):
-    for cond in conditions:
-        program, _, _ = cond
-        program.close()
     
 
 class ALUTestCase(FHDLTestCase):
-    def run_tst(self, conditions):
-        if not isinstance(conditions, list):
-            conditions = [conditions]
-        
+    def run_tst(self, program, initial_regs, initial_sprs):
         m = Module()
         comb = m.d.comb
         instruction = Signal(32)
@@ -89,55 +81,53 @@ class ALUTestCase(FHDLTestCase):
         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
         comb += alu.p.valid_i.eq(1)
         comb += alu.n.ready_i.eq(1)
+        simulator = ISA(pdecode2, initial_regs, initial_sprs)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)
+        gen = program.generate_instructions()
 
         sim.add_clock(1e-6)
         def process():
-            for cond in conditions:
-
-                program, initial_regs, initial_sprs = cond
-                gen = program.generate_instructions()
-                simulator = ISA(pdecode2, initial_regs, initial_sprs)
-                instructions = list(zip(gen, program.assembly.splitlines()))
-
+            instructions = list(zip(gen, program.assembly.splitlines()))
+
+            index = simulator.pc.CIA.value//4
+            while index < len(instructions):
+                ins, code = instructions[index]
+
+                print("0x{:X}".format(ins & 0xffffffff))
+                print(code)
+
+                # ask the decoder to decode this binary data (endian'd)
+                yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                yield instruction.eq(ins)          # raw binary instr.
+                yield Settle()
+                yield from set_alu_inputs(alu, pdecode2, simulator)
+                yield from set_extra_alu_inputs(alu, pdecode2, simulator)
+                yield 
+                opname = code.split(' ')[0]
+                yield from simulator.call(opname)
                 index = simulator.pc.CIA.value//4
-                while index < len(instructions):
-                    ins, code = instructions[index]
-
-                    print("0x{:X}".format(ins & 0xffffffff))
-                    print(code)
-
-                    # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
-                    yield instruction.eq(ins)          # raw binary instr.
-                    yield Settle()
-                    yield from set_alu_inputs(alu, pdecode2, simulator)
-                    yield from set_extra_alu_inputs(alu, pdecode2, simulator)
-                    yield 
-                    opname = code.split(' ')[0]
-                    yield from simulator.call(opname)
-                    index = simulator.pc.CIA.value//4
 
-                    vld = yield alu.n.valid_o
-                    while not vld:
-                        yield
-                        vld = yield alu.n.valid_o
+                vld = yield alu.n.valid_o
+                while not vld:
                     yield
-                    alu_out = yield alu.n.data_o.o
-                    out_reg_valid = yield pdecode2.e.write_reg.ok
-                    if out_reg_valid:
-                        write_reg_idx = yield pdecode2.e.write_reg.data
-                        expected = simulator.gpr(write_reg_idx).value
-                        print(f"expected {expected:x}, actual: {alu_out:x}")
-                        self.assertEqual(expected, alu_out)
-                    yield from self.check_extra_alu_outputs(alu, pdecode2,
-                                                            simulator)
+                    vld = yield alu.n.valid_o
+                yield
+                alu_out = yield alu.n.data_o.o
+                out_reg_valid = yield pdecode2.e.write_reg.ok
+                if out_reg_valid:
+                    write_reg_idx = yield pdecode2.e.write_reg.data
+                    expected = simulator.gpr(write_reg_idx).value
+                    print(f"expected {expected:x}, actual: {alu_out:x}")
+                    self.assertEqual(expected, alu_out)
+                yield from self.check_extra_alu_outputs(alu, pdecode2,
+                                                        simulator)
 
         sim.add_sync_process(process)
         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
                            traces=[]):
             sim.run()
+        return simulator
     def check_extra_alu_outputs(self, alu, dec2, sim):
         rc = yield dec2.e.rc.data
         if rc:
@@ -146,10 +136,11 @@ class ALUTestCase(FHDLTestCase):
             self.assertEqual(cr_expected, cr_actual)
 
     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
-        self.run_tst([(prog, initial_regs, initial_sprs)])
+        simulator = self.run_tst(prog, initial_regs, initial_sprs)
+        simulator.gpr.dump()
+        return simulator
 
     def test_rand(self):
-        conditions = []
         insns = ["add", "add.", "and", "or", "xor", "subf"]
         for i in range(40):
             choice = random.choice(insns)
@@ -157,12 +148,10 @@ class ALUTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
             initial_regs[2] = random.randint(0, (1<<64)-1)
-            conditions.append((Program(lst), initial_regs, {}))
-        self.run_tst(conditions)
-        cleanup_conditions(conditions)
+            with Program(lst) as program:
+                sim = self.run_tst_program(program, initial_regs)
 
     def test_rand_imm(self):
-        conditions = []
         insns = ["addi", "addis", "subfic"]
         for i in range(10):
             choice = random.choice(insns)
@@ -171,12 +160,10 @@ class ALUTestCase(FHDLTestCase):
             print(lst)
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
-            conditions.append((Program(lst), initial_regs, {}))
-        self.run_tst(conditions)
-        cleanup_conditions(conditions)
+            with Program(lst) as program:
+                sim = self.run_tst_program(program, initial_regs)
 
     def test_rand_imm_logical(self):
-        conditions = []
         insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
         for i in range(10):
             choice = random.choice(insns)
@@ -185,12 +172,10 @@ class ALUTestCase(FHDLTestCase):
             print(lst)
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
-            conditions.append((Program(lst), initial_regs, {}))
-        self.run_tst(conditions)
-        cleanup_conditions(conditions)
+            with Program(lst) as program:
+                sim = self.run_tst_program(program, initial_regs)
 
     def test_shift(self):
-        conditions = []
         insns = ["slw", "sld", "srw", "srd", "sraw", "srad"]
         for i in range(20):
             choice = random.choice(insns)
@@ -198,9 +183,9 @@ class ALUTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
             initial_regs[2] = random.randint(0, 63)
-            conditions.append((Program(lst), initial_regs, {}))
-        self.run_tst(conditions)
-        cleanup_conditions(conditions)
+            print(initial_regs[1], initial_regs[2])
+            with Program(lst) as program:
+                sim = self.run_tst_program(program, initial_regs)
 
 
     def test_shift_arith(self):
@@ -210,10 +195,9 @@ class ALUTestCase(FHDLTestCase):
         initial_regs[2] = random.randint(0, 63)
         print(initial_regs[1], initial_regs[2])
         with Program(lst) as program:
-            self.run_tst_program(program, initial_regs)
+            sim = self.run_tst_program(program, initial_regs)
 
     def test_rlwinm(self):
-        conditions = []
         for i in range(10):
             mb = random.randint(0,31)
             me = random.randint(0,31)
@@ -221,9 +205,8 @@ class ALUTestCase(FHDLTestCase):
             lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}"]
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
-            conditions.append((Program(lst), initial_regs, {}))
-        self.run_tst(conditions)
-        cleanup_conditions(conditions)
+            with Program(lst) as program:
+                sim = self.run_tst_program(program, initial_regs)
 
     def test_rlwimi(self):
         lst = ["rlwimi 3, 1, 5, 20, 6"]
@@ -231,7 +214,7 @@ class ALUTestCase(FHDLTestCase):
         initial_regs[1] = 0xdeadbeef
         initial_regs[3] = 0x12345678
         with Program(lst) as program:
-            self.run_tst_program(program, initial_regs)
+            sim = self.run_tst_program(program, initial_regs)
 
     def test_rlwnm(self):
         lst = ["rlwnm 3, 1, 2, 20, 6"]
@@ -239,7 +222,7 @@ class ALUTestCase(FHDLTestCase):
         initial_regs[1] = random.randint(0, (1<<64)-1)
         initial_regs[2] = random.randint(0, 63)
         with Program(lst) as program:
-            self.run_tst_program(program, initial_regs)
+            sim = self.run_tst_program(program, initial_regs)
         
     def test_adde(self):
         lst = ["adde. 5, 6, 7"]
@@ -251,7 +234,7 @@ class ALUTestCase(FHDLTestCase):
         xer[XER_bits['CA']] = 1
         initial_sprs[special_sprs['XER']] = xer
         with Program(lst) as program:
-            self.run_tst_program(program, initial_regs, initial_sprs)
+            sim = self.run_tst_program(program, initial_regs, initial_sprs)
 
     def test_ilang(self):
         rec = CompALUOpSubset()