allow imem to be 64/32 bit wide

diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py
index 74d6d8e6e002de66e8e15e780c317c054981d554..2022127592c1b5c5ee8bb30c7a7cab84983f5014 100644 (file)
--- a/src/soc/minerva/units/fetch.py
+++ b/src/soc/minerva/units/fetch.py
@@ -12,8 +12,11 @@ class FetchUnitInterface:
     def __init__(self, pspec):
         self.pspec = pspec
         self.addr_wid = pspec.addr_wid
-        self.data_wid = pspec.reg_wid
-        self.adr_lsbs = log2_int(pspec.reg_wid//8)
+        if isinstance(pspec.imem_reg_wid, int):
+            self.data_wid = pspec.imem_reg_wid
+        else:
+            self.data_wid = pspec.reg_wid
+        self.adr_lsbs = log2_int(self.data_wid//8)
         self.ibus = Record(make_wb_layout(pspec))
         bad_wid = pspec.addr_wid - self.adr_lsbs # TODO: is this correct?
 

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 1b8d82ebffc7ea348305a874798bd2f6a22f2d7a..9de80a5179dde191af08e3716cc2b52ace10bdfe 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -150,7 +150,11 @@ class TestIssuer(Elaboratable):
                         comb += self.imem.f_valid_i.eq(1)
                     with m.Else():
                         # not busy: instruction fetched
-                        insn = self.imem.f_instr_o.word_select(cur_pc[2], 32)
+                        f_instr_o = self.imem.f_instr_o
+                        if f_instr_o.width == 32:
+                            insn = f_instr_o
+                        else:
+                            insn = f_instr_o.word_select(cur_pc[2], 32)
                         comb += current_insn.eq(insn)
                         comb += core_ivalid_i.eq(1) # instruction is valid
                         comb += core_issue_i.eq(1)  # and issued