def eq(self, rhs):
""" Assign member signals. """
- print (self, rhs)
+ #print (self, rhs)
return DivPipeCoreInterstageData.eq(self, rhs) + \
DivPipeBaseData.eq(self, rhs)
def __init__(self, pspec):
self.pspec = pspec
- print ("DivPipeSetupStage", pspec, pspec.core_config)
+ #print ("DivPipeSetupStage", pspec, pspec.core_config)
DivPipeCoreSetupStage.__init__(self, pspec.core_config)
def ispec(self):
def __init__(self, pspec, e_extra=False):
FPState.__init__(self, "normalise_1")
- print ("normtopack", pspec)
+ #print ("normtopack", pspec)
self.pspec = pspec
self.e_extra = e_extra
SimpleHandshake.__init__(self, self) # pipeline is its own stage
def test_pipe_sqrt_fp16():
dut = FPDIVMuxInOut(16, 4)
runfp(dut, 16, "test_fpsqrt_pipe_fp16", Float16, sqrt,
- single_op=True, opcode=1)
+ single_op=True, opcode=1, n_vals=100)
def test_pipe_sqrt_fp32():
dut = FPDIVMuxInOut(32, 4)
runfp(dut, 32, "test_fpsqrt_pipe_fp32", Float32, sqrt,
- single_op=True, opcode=1)
+ single_op=True, opcode=1, n_vals=100)
def test_pipe_sqrt_fp64():
dut = FPDIVMuxInOut(64, 4)
runfp(dut, 64, "test_fpsqrt_pipe_fp64", Float64, sqrt,
- single_op=True, opcode=1)
+ single_op=True, opcode=1, n_vals=100)
if __name__ == '__main__':
test_pipe_sqrt_fp16()