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arg CacheRam read output needs delay by 1 cycle
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 1 Oct 2020 17:39:58 +0000 (18:39 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 1 Oct 2020 17:39:58 +0000 (18:39 +0100)
src/soc/experiment/dcache.py patch | blob | history

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index b3d0b76fb3112a8f47444473c76a93bed97cdb9e..5f96e04a94a72733a8e576af7df432048b93c370 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1073,7 +1073,7 @@ class DCache(Elaboratable):
             wr_sel_m = Signal(ROW_SIZE)
             _d_out   = Signal(WB_DATA_BITS, name="dout_%d" % i)
 
-            way = CacheRam(ROW_BITS, WB_DATA_BITS, True)
+            way = CacheRam(ROW_BITS, WB_DATA_BITS, ADD_BUF=True)
             setattr(m.submodules, "cacheram_%d" % i, way)
 
             comb += way.rd_en.eq(do_read)