DESIGN_KIT = FreePDK_C4M45
YOSYS_FLATTEN = No
YOSYS_BLACKBOXES = pll \
- spblock512w64b8w_0 \
- spblock512w64b8w_1 \
- spblock512w64b8w_2 \
- spblock512w64b8w_3
+ spblock_512w64b8w
# YOSYS_SET_TOP = Yes
CHIP = chip
CORE = ls180
-<* blackbox = 1 *)
+(* blackbox = 1 *)
module spblock_512w64b8w(a, d, q, we, clk);
input [8:0] a;
input [63:0] d;
# DESIGN_KIT = cmos45
YOSYS_FLATTEN = No
YOSYS_BLACKBOXES = pll \
- spblock512w64b8w_0 \
- spblock512w64b8w_1 \
- spblock512w64b8w_2 \
- spblock512w64b8w_3
+ spblock_512w64b8w
# YOSYS_SET_TOP = Yes
CHIP = chip
CORE = ls180