fix incompatibility between spec gen and pinmux code-gen

diff --git a/src/spec/gen.py b/src/spec/gen.py
index 3c66f34a7c8412caa90ac9b87debe5e51e97b130..d398384480775ccd99af039e5edc9e02655caaa6 100644 (file)
--- a/src/spec/gen.py
+++ b/src/spec/gen.py
@@ -20,15 +20,15 @@ def specgen(pth, pinouts, bankspec, fixedpins):
             with open(os.path.join(pth, '%s.txt' % k.lower()), 'w') as g:
                 if len(s0.pingroup) == 1:  # only one function, grouped higher
                     for ks in s.keys():  # grouped by interface
+                        fntype = 'inout' # XXX TODO
                         k = "%s_%s" % (s[ks].fname, s[ks].suffix)
                         k_ = k.lower()
                         g.write("%s\t%s\n" % (k_, fntype))
                 else:
                     for pinname in s0.pingroup:
                         fntype = s0.fntype.get(pinname, 'inout')
-                        k_ = k.lower()
                         pn = pinname.lower()
-                        g.write("%s_%s\t%s\n" % (k_, pn, fntype))
+                        g.write("%s\t%s\n" % (pn, fntype))
 
     pks = pinouts.keys()
     pks.sort()

diff --git a/src/spec/ifaceprint.py b/src/spec/ifaceprint.py
index d8008c7feb14734786ca6ce8bf7456289bec5cc3..57159091cdb709825301e5063f9611ad9a99815b 100644 (file)
--- a/src/spec/ifaceprint.py
+++ b/src/spec/ifaceprint.py
@@ -171,7 +171,7 @@ def check_functions(title, bankspec, fns, pins, required, eint, pwm,
             if descriptions and descriptions.has_key(fname):
                 desc = ': %s' % descriptions[fname]
             bank = fname[4]
-            pin = int(fname[5:])
+            pin = int(fname[7:])
             pin_ = pin + bankspec[bank]
             if not pins.has_key(pin_):
                 continue

diff --git a/src/spec/interfaces.py b/src/spec/interfaces.py
index 0f8e1da12e4bdb8a86b01b9e1cc44c6f326134d5..891a12311f5d66da6932c5368b8b040d6b150fa5 100644 (file)
--- a/src/spec/interfaces.py
+++ b/src/spec/interfaces.py
@@ -1,6 +1,5 @@
 #!/usr/bin/env python
 
-
 class Pinouts(object):
     def __init__(self):
         self.pins = {}
@@ -40,7 +39,7 @@ class Pinouts(object):
 class Pins(object):
 
     def __init__(self, fname, pingroup, bankspec, suffix, offs, bank, mux,
-                 spec=None, limit=None, origsuffix=None):
+             spec=None, limit=None, origsuffix=None):
 
         # function type can be in, out or inout, represented by - + *
         # strip function type out of each pin name
@@ -67,7 +66,7 @@ class Pins(object):
 
         # create consistent name suffixes
         pingroup = namesuffix(fname, suffix, pingroup)
-        suffix = ''  # hack
+        suffix = '' # hack
 
         res = {}
         names = {}
@@ -108,12 +107,11 @@ class Pins(object):
 
 def i2s(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
     i2spins = ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
-    # for i in range(4):
+    #for i in range(4):
     #    i2spins.append("DO%d+" % i)
     return Pins('IIS', i2spins, bankspec, suffix, offs, bank, mux, spec, limit,
                 origsuffix=suffix)
 
-
 def emmc(bankspec, suffix, offs, bank, mux=1, spec=None):
     emmcpins = ['CMD+', 'CLK+']
     for i in range(8):
@@ -121,9 +119,8 @@ def emmc(bankspec, suffix, offs, bank, mux=1, spec=None):
     return Pins('MMC', emmcpins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def sdmmc(bankspec, suffix, offs, bank, mux=1, spec=None,
-          start=None, limit=None):
+                start=None, limit=None):
     sdmmcpins = ['CMD+', 'CLK+']
     for i in range(4):
         sdmmcpins.append("D%d*" % i)
@@ -131,37 +128,31 @@ def sdmmc(bankspec, suffix, offs, bank, mux=1, spec=None,
     return Pins('SD', sdmmcpins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def spi(bankspec, suffix, offs, bank, mux=1, spec=None):
     spipins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
     return Pins('SPI', spipins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def quadspi(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
     spipins = ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
     return Pins('QSPI', spipins, bankspec, suffix, offs, bank, mux, spec, limit,
                 origsuffix=suffix)
 
-
 def i2c(bankspec, suffix, offs, bank, mux=1, spec=None):
     spipins = ['SDA*', 'SCL*']
     return Pins('TWI', spipins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def jtag(bankspec, suffix, offs, bank, mux=1, spec=None):
     jtagpins = ['MS+', 'DI-', 'DO+', 'CK+']
     return Pins('JTAG', jtagpins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def uart(bankspec, suffix, offs, bank, mux=1, spec=None):
     uartpins = ['TX+', 'RX-']
     return Pins('UART', uartpins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def namesuffix(name, suffix, namelist):
     names = []
     for n in namelist:
@@ -171,7 +162,6 @@ def namesuffix(name, suffix, namelist):
             names.append("%s_%s" % (name, suffix))
     return names
 
-
 def ulpi(bankspec, suffix, offs, bank, mux=1, spec=None):
     ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
     for i in range(8):
@@ -179,13 +169,11 @@ def ulpi(bankspec, suffix, offs, bank, mux=1, spec=None):
     return Pins('ULPI', ulpipins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def uartfull(bankspec, suffix, offs, bank, mux=1, spec=None):
     uartpins = ['TX+', 'RX-', 'CTS-', 'RTS+']
     return Pins('UARTQ', uartpins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def rgbttl(bankspec, suffix, offs, bank, mux=1, spec=None):
     ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
     for i in range(24):
@@ -193,7 +181,6 @@ def rgbttl(bankspec, suffix, offs, bank, mux=1, spec=None):
     return Pins('LCD', ttlpins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def rgmii(bankspec, suffix, offs, bank, mux=1, spec=None):
     buspins = []
     for i in range(4):
@@ -207,7 +194,6 @@ def rgmii(bankspec, suffix, offs, bank, mux=1, spec=None):
     return Pins('RG', buspins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def flexbus1(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
     buspins = []
     for i in range(8):
@@ -219,20 +205,18 @@ def flexbus1(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
                 'TSIZ0', 'TSIZ1']
     for i in range(4):
         buspins.append("BWE%d" % i)
-    for i in range(2, 6):
+    for i in range(2,6):
         buspins.append("CS%d+" % i)
     return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
                 origsuffix=suffix)
 
-
 def flexbus2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
     buspins = []
-    for i in range(8, 32):
+    for i in range(8,32):
         buspins.append("AD%d*" % i)
     return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
                 origsuffix=suffix)
 
-
 def sdram1(bankspec, suffix, offs, bank, mux=1, spec=None):
     buspins = []
     for i in range(16):
@@ -252,17 +236,15 @@ def sdram1(bankspec, suffix, offs, bank, mux=1, spec=None):
     return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def sdram2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
     buspins = []
-    for i in range(3, 6):
+    for i in range(3,6):
         buspins.append("SDRCS%d#+" % i)
-    for i in range(8, 32):
+    for i in range(8,32):
         buspins.append("SDRDQ%d*" % i)
     return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
                 origsuffix=suffix)
 
-
 def mcu8080(bankspec, suffix, offs, bank, mux=1, spec=None):
     buspins = []
     for i in range(8):
@@ -278,16 +260,14 @@ def mcu8080(bankspec, suffix, offs, bank, mux=1, spec=None):
     return Pins('MCU', buspins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def _pinbank(bankspec, prefix, suffix, offs, bank, gpiooffs, gpionum=1, mux=1,
              spec=None):
     gpiopins = []
     for i in range(gpiooffs, gpiooffs+gpionum):
         gpiopins.append("%s%d*" % (bank, i))
-    return Pins('GPIO', gpiopins, bankspec, suffix, offs, bank, mux, spec,
+    return Pins(prefix, gpiopins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def eint(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
     gpiopins = []
     for i in range(gpiooffs, gpiooffs+gpionum):
@@ -295,17 +275,14 @@ def eint(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
     return Pins('EINT', gpiopins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def pwm(bankspec, suffix, offs, bank, mux=1, spec=None):
     return Pins('PWM', ['+', ], bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
-
 def gpio(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
-    return _pinbank(bankspec, "GPIO", suffix, offs, bank, gpiooffs,
+    return _pinbank(bankspec, "GPIO%s" % bank, suffix, offs, bank, gpiooffs,
                               gpionum, mux=0, spec=None)
 
-
 def pinmerge(pins, fn):
     # hack, store the function specs in the pins dict
     fname = fn.fname
@@ -326,7 +303,8 @@ def pinmerge(pins, fn):
         specname = fname + bank
     pins.fnspec[fname][specname] = fn
 
+
     # merge actual pins
     for (pinidx, v) in fn.pins.items():
-        print "pinidx", pinidx
         pins.update(pinidx, v)
+

diff --git a/src/spec/m_class.py b/src/spec/m_class.py
index a9c09a86c6e6cecc876958ca7acb197251b5add1..9ec198c7728ad49fc10431c7e9826b8651ee49e0 100644 (file)
--- a/src/spec/m_class.py
+++ b/src/spec/m_class.py
@@ -530,19 +530,19 @@ def pinspec():
                 'MCU EINT-capable GPIO may be used to generate extra EINTs\n'
                 'on the single MCU_INT line, if really needed',
         'F2:PWM_0': 'LCD Backlight',
-        'GPIOD4': 'WL_WAKE_AP',
-        'GPIOD5': 'BT_WAKE_AP',
-        'GPIOD6': 'AP_WAKE_BT',
-        'GPIOD7': 'AP_CK32KO',
-        'GPIOD8': 'HSPA_PWRON',
-        'GPIOD9': 'BT_RST_N',
-        'GPIOE5': 'HSPA_ON_OFF',
-        'GPIOD2': 'HSPA_SHUTDOWN',
-        'GPIOD3': 'CTP_RST',
-        'GPIOD12': 'LCD_RDN',
-        'GPIOD17': 'LCD_WRN',
-        'GPIOD18': 'LCD_RS',
-        'GPIOD21': 'LCD_CSN',
+        'GPIOD_D4': 'WL_WAKE_AP',
+        'GPIOD_D5': 'BT_WAKE_AP',
+        'GPIOD_D6': 'AP_WAKE_BT',
+        'GPIOD_D7': 'AP_CK32KO',
+        'GPIOD_D8': 'HSPA_PWRON',
+        'GPIOD_D9': 'BT_RST_N',
+        'GPIOE_E5': 'HSPA_ON_OFF',
+        'GPIOD_D2': 'HSPA_SHUTDOWN',
+        'GPIOD_D3': 'CTP_RST',
+        'GPIOD_D12': 'LCD_RDN',
+        'GPIOD_D17': 'LCD_WRN',
+        'GPIOD_D18': 'LCD_RS',
+        'GPIOD_D21': 'LCD_CSN',
 
         'EINT_5': 'HSPA_MST_RDY',
         'EINT_6': 'HSPA_SL_RDY',