remove redundant code

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index b358b49069f9a6528f3d03ceb845957b6ac033ee..5279953c5820ff258b5f3b842bed310fbdcc072c 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -520,10 +520,6 @@ class ICache(Elaboratable):
             comb += req_is_hit.eq(is_hit)
             comb += req_is_miss.eq(~is_hit)
 
-        with m.Else():
-            comb += req_is_hit.eq(0)
-            comb += req_is_miss.eq(0)
-
         comb += req_hit_way.eq(hit_way)
 
         # The way to replace on a miss