/* Add special gl_VertexID/gl_InstanceID buffers */
+ struct mali_attr_meta hw[PIPE_MAX_ATTRIBS];
+
panfrost_vertex_id(ctx->padded_count, &attrs[k]);
- so->hw[PAN_VERTEX_ID].index = k++;
+ hw[PAN_VERTEX_ID].index = k++;
+ hw[PAN_VERTEX_ID].format = so->formats[PAN_VERTEX_ID];
+ hw[PAN_VERTEX_ID].unknown1 = 0x2;
+
panfrost_instance_id(ctx->padded_count, &attrs[k]);
- so->hw[PAN_INSTANCE_ID].index = k++;
+ hw[PAN_INSTANCE_ID].index = k++;
+ hw[PAN_INSTANCE_ID].format = so->formats[PAN_VERTEX_ID];
+ hw[PAN_INSTANCE_ID].unknown1 = 0x2;
/* Attribute addresses require 64-byte alignment, so let:
*
if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start)
src_offset -= buf->stride * start;
- so->hw[i].src_offset = src_offset;
- so->hw[i].index = attrib_to_buffer[i];
+ hw[i].src_offset = src_offset;
+ hw[i].index = attrib_to_buffer[i];
+ hw[i].format = so->formats[i];
+ hw[i].unknown1 = 0x2;
}
vertex_postfix->attributes = panfrost_pool_upload(&batch->pool, attrs,
k * sizeof(*attrs));
- vertex_postfix->attribute_meta = panfrost_pool_upload(&batch->pool, so->hw,
- sizeof(*so->hw) *
+ vertex_postfix->attribute_meta = panfrost_pool_upload(&batch->pool, hw,
+ sizeof(hw[0]) *
PAN_MAX_ATTRIBUTE);
}
memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
for (int i = 0; i < num_elements; ++i) {
- so->hw[i].index = i;
-
enum pipe_format fmt = elements[i].src_format;
const struct util_format_description *desc = util_format_description(fmt);
- so->hw[i].unknown1 = 0x2;
-
unsigned swizzle = 0;
if (dev->quirks & HAS_SWIZZLES)
swizzle = panfrost_translate_swizzle_4(desc->swizzle);
swizzle = panfrost_bifrost_swizzle(desc->nr_channels);
enum mali_format hw_format = panfrost_pipe_format_table[desc->format].hw;
- so->hw[i].format = (hw_format << 12) | swizzle;
+ so->formats[i] = (hw_format << 12) | swizzle;
assert(hw_format);
}
/* Let's also prepare vertex builtins */
- so->hw[PAN_VERTEX_ID].format = MALI_R32UI;
if (dev->quirks & HAS_SWIZZLES)
- so->hw[PAN_VERTEX_ID].format = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
+ so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
else
- so->hw[PAN_VERTEX_ID].format = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
+ so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
if (dev->quirks & HAS_SWIZZLES)
- so->hw[PAN_INSTANCE_ID].format = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
+ so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
else
- so->hw[PAN_INSTANCE_ID].format = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
+ so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
return so;
}
unsigned num_elements;
struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
- struct mali_attr_meta hw[PIPE_MAX_ATTRIBS];
+ unsigned formats[PIPE_MAX_ATTRIBS];
};
struct panfrost_zsa_state {