Add simple register tests.

Make the RegsTest case a bit more comprehensible.

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 163b136c272ec14660d546d45f37da2c5c4cb58b..27c3ad4e8e5c61d7c787d5e049d72b19a8bbc733 100755 (executable)
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -39,7 +39,45 @@ class DeleteServer(unittest.TestCase):
     def tearDown(self):
         del self.server
 
-class MemoryTest(DeleteServer):
+class SimpleRegisterTest(DeleteServer):
+    def setUp(self):
+        self.server = target.server()
+        self.gdb = testlib.Gdb()
+        self.gdb.command("target extended-remote localhost:%d" % self.server.port)
+
+        # 0x13 is nop
+        self.gdb.command("p *((int*) 0x%x)=0x13" % target.ram)
+        self.gdb.command("p *((int*) 0x%x)=0x13" % (target.ram + 4))
+        self.gdb.command("p *((int*) 0x%x)=0x13" % (target.ram + 8))
+        self.gdb.p("$pc=0x%x" % target.ram)
+
+    def check_reg(self, name):
+        a = random.randrange(1<<target.xlen)
+        b = random.randrange(1<<target.xlen)
+        self.gdb.p("$%s=0x%x" % (name, a))
+        self.gdb.stepi()
+        self.assertEqual(self.gdb.p("$%s" % name), a)
+        self.gdb.p("$%s=0x%x" % (name, b))
+        self.gdb.stepi()
+        self.assertEqual(self.gdb.p("$%s" % name), b)
+
+    def test_s0(self):
+        # S0 is saved/restored in DSCRATCH
+        self.check_reg("s0")
+
+    def test_s1(self):
+        # S1 is saved/restored in Debug RAM
+        self.check_reg("s1")
+
+    def test_t0(self):
+        # T0 is not saved/restored at all
+        self.check_reg("t2")
+
+    def test_t2(self):
+        # T2 is not saved/restored at all
+        self.check_reg("t2")
+
+class SimpleMemoryTest(DeleteServer):
     def setUp(self):
         self.server = target.server()
         self.gdb = testlib.Gdb()
@@ -211,17 +249,12 @@ class RegsTest(DeleteServer):
         self.gdb.c()
 
     def test_write_gprs(self):
-        # Note a0 is missing from this list since it's used to hold the
-        # address.
-        regs = ("ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1",
-                "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4",
-                "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5",
-                "t6")
+        regs = [("x%d" % n) for n in range(2, 32)]
 
         self.gdb.p("$pc=write_regs")
         for i, r in enumerate(regs):
             self.gdb.command("p $%s=%d" % (r, (0xdeadbeef<<i)+17))
-        self.gdb.command("p $a0=data")
+        self.gdb.command("p $x1=data")
         self.gdb.command("b all_done")
         output = self.gdb.c()
         self.assertIn("Breakpoint ", output)
@@ -231,7 +264,7 @@ class RegsTest(DeleteServer):
         self.gdb.command("info registers")
         for n in range(len(regs)):
             self.assertEqual(self.gdb.x("data+%d" % (8*n), 'g'),
-                    (0xdeadbeef<<n)+17)
+                    ((0xdeadbeef<<n)+17) & ((1<<target.xlen)-1))
 
     def test_write_csrs(self):
         # As much a test of gdb as of the simulator.

diff --git a/debug/programs/regs.S b/debug/programs/regs.S
index 989d037ceb6c6e474a1eb8ebee1ed33d05355a04..2cacd4f92ff225e56e012ad7bc485b1ec510358a 100644 (file)
--- a/debug/programs/regs.S
+++ b/debug/programs/regs.S
@@ -12,39 +12,40 @@
 
         .global main
 main:
+        nop
         j       main
 
 write_regs:
-        SREG    x1, 0(a0)
-        SREG    x2, 8(a0)
-        SREG    x3, 16(a0)
-        SREG    x4, 24(a0)
-        SREG    x5, 32(a0)
-        SREG    x6, 40(a0)
-        SREG    x7, 48(a0)
-        SREG    x8, 56(a0)
-        SREG    x9, 64(a0)
-        SREG    x11, 72(a0)
-        SREG    x12, 80(a0)
-        SREG    x13, 88(a0)
-        SREG    x14, 96(a0)
-        SREG    x15, 104(a0)
-        SREG    x16, 112(a0)
-        SREG    x17, 120(a0)
-        SREG    x18, 128(a0)
-        SREG    x19, 136(a0)
-        SREG    x20, 144(a0)
-        SREG    x21, 152(a0)
-        SREG    x22, 160(a0)
-        SREG    x23, 168(a0)
-        SREG    x24, 176(a0)
-        SREG    x25, 184(a0)
-        SREG    x26, 192(a0)
-        SREG    x27, 200(a0)
-        SREG    x28, 208(a0)
-        SREG    x29, 216(a0)
-        SREG    x30, 224(a0)
-        SREG    x31, 232(a0)
+        SREG    x2, 0(x1)
+        SREG    x3, 8(x1)
+        SREG    x4, 16(x1)
+        SREG    x5, 24(x1)
+        SREG    x6, 32(x1)
+        SREG    x7, 40(x1)
+        SREG    x8, 48(x1)
+        SREG    x9, 56(x1)
+        SREG    x10, 64(x1)
+        SREG    x11, 72(x1)
+        SREG    x12, 80(x1)
+        SREG    x13, 88(x1)
+        SREG    x14, 96(x1)
+        SREG    x15, 104(x1)
+        SREG    x16, 112(x1)
+        SREG    x17, 120(x1)
+        SREG    x18, 128(x1)
+        SREG    x19, 136(x1)
+        SREG    x20, 144(x1)
+        SREG    x21, 152(x1)
+        SREG    x22, 160(x1)
+        SREG    x23, 168(x1)
+        SREG    x24, 176(x1)
+        SREG    x25, 184(x1)
+        SREG    x26, 192(x1)
+        SREG    x27, 200(x1)
+        SREG    x28, 208(x1)
+        SREG    x29, 216(x1)
+        SREG    x30, 224(x1)
+        SREG    x31, 232(x1)
 
         csrr    x1, CSR_MSCRATCH
 

diff --git a/debug/targets/m2gl_m2s/openocd.cfg b/debug/targets/m2gl_m2s/openocd.cfg
index 0e1a4916800761dc545d256be63773a6bf40e7e1..da20ccc09bf6f4f3edf3eb81a04b87cf288bd4af 100644 (file)
--- a/debug/targets/m2gl_m2s/openocd.cfg
+++ b/debug/targets/m2gl_m2s/openocd.cfg
@@ -16,4 +16,4 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 init
 #reset
 
-#halt
+halt

diff --git a/debug/testlib.py b/debug/testlib.py
index bb604a7dcf4928f55dee37b91642c3c0c3a4faef..f654d437d0cb0655458ef983b6a44290545cc51a 100644 (file)
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -48,7 +48,7 @@ class Spike(object):
             cmd = shlex.split(cmd)
         else:
             cmd = ["spike"]
-        #cmd.append("-l")    #<<<
+        cmd.append("-l")    #<<<
 
         if timeout:
             cmd = ["timeout", str(timeout)] + cmd
@@ -150,7 +150,7 @@ class Gdb(object):
         return output
 
     def load(self):
-        output = self.command("load", timeout=120)
+        output = self.command("load")
         assert "failed" not in  output
         assert "Transfer rate" in output