update CROutputData to use Data()

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index 607579d17f65a6cb69260d8841186496e78b4b71..efb821e5bcee6588357d5a638d0b7b5225a295f5 100644 (file)
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -36,11 +36,11 @@ class CRMainStage(PipeModBase):
         op = self.i.ctx.op
         a, full_cr = self.i.a, self.i.full_cr
         cr_a, cr_b, cr_c = self.i.cr_a, self.i.cr_b, self.i.cr_c
+        cr_o, full_cr_o, rt_o = self.o.cr_o, self.o.full_cr, self.o.o
+
         xl_fields = self.fields.FormXL
         xfx_fields = self.fields.FormXFX
 
-        cr_o = self.o.cr_o
-
         # Generate the mask for mtcrf, mtocrf, and mfocrf
         # replicate every fxm field in the insn to 4-bit, as a mask
         FXM = xfx_fields.FXM[0:-1]
@@ -52,9 +52,6 @@ class CRMainStage(PipeModBase):
         cr_b_arr = Array([cr_b[i] for i in range(4)])
         cr_o_arr = Array([cr_o[i] for i in range(4)])
 
-        # this may have one bit be modified by OP_CROP
-        comb += cr_o.eq(cr_c)
-
         with m.Switch(op.insn_type):
             ##### mcrf #####
             with m.Case(InternalOp.OP_MCRF):
@@ -63,6 +60,7 @@ class CRMainStage(PipeModBase):
                 # Since it takes in a 4 bit cr, and outputs a 4 bit
                 # cr, we don't have to do anything special
                 comb += cr_o.eq(cr_a)
+                comb += cr_o.ok.eq(1) # indicate "this CR has changed"
 
             # ##### crand, cror, crnor etc. #####
             with m.Case(InternalOp.OP_CROP):
@@ -104,15 +102,19 @@ class CRMainStage(PipeModBase):
                                      Mux(bit_a, lut[3], lut[1]),
                                      Mux(bit_a, lut[2], lut[0])))
 
-                # insert the output bit into the 4-bit CR output
+                # may have one bit modified by OP_CROP. copy the other 3
+                comb += cr_o.data.eq(cr_c)
+                # insert the (index-targetted) output bit into 4-bit CR output
                 comb += cr_o_arr[bt].eq(bit_o)
+                comb += cr_o.ok.eq(1) # indicate "this CR has changed"
 
             ##### mtcrf #####
             with m.Case(InternalOp.OP_MTCRF):
                 # mtocrf and mtcrf are essentially identical
                 # put input (RA) - mask-selected - into output CR, leave
                 # rest of CR alone.
-                comb += self.o.full_cr.eq((a[0:32] & mask) | (full_cr & ~mask))
+                comb += full_cr_o.data.eq((a[0:32] & mask) | (full_cr & ~mask))
+                comb += full_cr_o.ok.eq(1) # indicate "this CR has changed"
 
             # ##### mfcr #####
             with m.Case(InternalOp.OP_MFCR):
@@ -125,11 +127,11 @@ class CRMainStage(PipeModBase):
                 # mfocrf
                 with m.If(move_one):
                     # output register RT
-                    comb += self.o.o.eq(full_cr & mask)
+                    comb += rt_o.eq(full_cr & mask)
                 # mfcrf
                 with m.Else():
                     # output register RT
-                    comb += self.o.o.eq(full_cr)
+                    comb += rt_o.eq(full_cr)
 
         comb += self.o.ctx.eq(self.i.ctx)
 

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index 4066ae0907e60108ae1df98484576c3c2d1548e3..e59a81ebe2b00af390ede2c4c04674856dbfa61c 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -2,6 +2,7 @@ from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
+from soc.decoder.power_decoder2 import Data
 
 
 class CRInputData(IntegerData):
@@ -42,8 +43,8 @@ class CROutputData(IntegerData):
     def __init__(self, pspec):
         super().__init__(pspec)
         self.o = Signal(64, reset_less=True) # RA
-        self.full_cr = Signal(32, reset_less=True, name="cr_out") # CR in
-        self.cr_o = Signal(4, reset_less=True)
+        self.full_cr = Data(32, name="cr_out") # CR in
+        self.cr_o = Data(4, name="cr_o")
 
     def __iter__(self):
         yield from super().__iter__()

diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index daa16180fa07c3cc1c0e04783eab6a7ab5c79d8f..67b67b6e48c929250430687e867958f4e1963fc5 100644 (file)
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -160,13 +160,13 @@ class TestRunner(FHDLTestCase):
         whole_reg = yield dec2.e.write_cr_whole
         cr_en = yield dec2.e.write_cr.ok
         if whole_reg:
-            full_cr = yield alu.n.data_o.full_cr
+            full_cr = yield alu.n.data_o.full_cr.data
             expected_cr = simulator.cr.get_range().value
             self.assertEqual(expected_cr, full_cr)
         elif cr_en:
             cr_sel = yield dec2.e.write_cr.data
             expected_cr = simulator.crl[cr_sel].get_range().value
-            real_cr = yield alu.n.data_o.cr_o
+            real_cr = yield alu.n.data_o.cr_o.data
             self.assertEqual(expected_cr, real_cr)