ddrphy_addr, dramcore_addr,
ddr_addr, fw_addr=0x0000_0000,
firmware=None,
- clk_freq=40e6):
+ clk_freq=50e6):
# set up wishbone bus arbiter and decoder. arbiter routes,
# decoder maps local-relative addressed satellites to global addresses
self.ram = SRAMPeripheral(size=4096)
self._decoder.add(self.ram.bus, addr=0x8000000) # SRAM at 0x8000_0000
- # UART at 0xC000_2000
+ # UART at 0xC000_2000, convert 32-bit bus down to 8-bit
if uart_pins is not None:
- self.uart = UART16550()
- umap = MemoryMap(addr_width=7, data_width=8, name="uart_map")
- #umap.add_resource(self._mem, name="mem", size=1<<5)
- self.uart.bus.memory_map = umap
- self._decoder.add(self.uart.bus, addr=0xc0002000) # 16550 UART addr
+ if True:
+ self.uart = uart = UART16550()
+ umap = MemoryMap(addr_width=7, data_width=8, name="uart_map")
+ uart.bus.memory_map = umap
+ self._decoder.add(uart.bus, addr=0xc0002000) # 16550 UART addr
+ else:
+ self.uart = UART16550(data_width=8)
+ cvtuartbus = wishbone.Interface(addr_width=3, data_width=32,
+ granularity=8)
+ self.uartdowncvt = WishboneDownConvert(cvtuartbus,
+ self.uart.bus)
+ umap = MemoryMap(addr_width=5, data_width=8, name="uart_map")
+ cvtuartbus.memory_map = umap
+ self._decoder.add(cvtuartbus, addr=0xc0002000) # 16550 UART addr
# DRAM Module
if ddr_pins is not None:
m.submodules.bootmem = self.bootmem
m.submodules.syscon = self.syscon
m.submodules.ram = self.ram
- m.submodules.uart = self.uart
+ if hasattr(self, "uart"):
+ m.submodules.uart = self.uart
+ comb += self.uart.cts_i.eq(1)
+ comb += self.uart.dsr_i.eq(1)
+ comb += self.uart.ri_i.eq(0)
+ comb += self.uart.dcd_i.eq(1)
+ if hasattr(self, "uartdowncvt"):
+ m.submodules.uartdowncvt = self.uartdowncvt
m.submodules.arbiter = self._arbiter
m.submodules.decoder = self._decoder
if hasattr(self, "ddrphy"):