use nmigen_boards naming conventions for SPIFlash

diff --git a/src/ls2.py b/src/ls2.py
index 98fe67b79e8c75a9abef67605348ee21e6441d99..82186e2f3991818fbd312553da6ec221eddd71de 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -532,6 +532,7 @@ class DDR3SoC(SoC, Elaboratable):
             # add Tercel verilog source. assumes a directory structure where
             # microwatt has been checked out in a common subdirectory with:
             # git clone https://git.libre-soc.org/git/microwatt.git tercel-qspi
+            # git checkout 882ace781e4
             raptor_tercel = "../../tercel-qspi/tercel"
             pth = os.path.split(__file__)[0]
             pth = os.path.join(pth, raptor_tercel)
@@ -658,15 +659,19 @@ def build_platform(fpga, firmware):
 
     # Get SPI resource pins
     spi_0_pins = None
-    if platform is not None and fpga in ['rcs_arctic_tern_bmc_card']:
+    if platform is not None and fpga in ['rcs_arctic_tern_bmc_card',
+                                         'arty_a7']:
+        # XXX naming-conventions for nmigen_boards/resources/interface.py
+        # SPIResource are "spi" not "spi_0", and for SPIFlashResources
+        # the name convention is "spi_flash_1x" (or 2x or 4x)
         if toolchain == 'Trellis':
             # The ECP5 series FPGAs handle the SPI clock directly on
             # the FPGA configuration Flash device
-            spi_0_pins = platform.request("spi_0", 0,
+            spi_0_pins = platform.request("spi_flash_4x", 0,
                                         dir={"dq":"io", "cs_n":"o"},
                                         xdr={"dq": 1, "cs_n": 1})
         else:
-            spi_0_pins = platform.request("spi_0", 0,
+            spi_0_pins = platform.request("spi_flash_4x", 0,
                                         dir={"dq":"io", "cs_n":"o", "clk":"o"},
                                         xdr={"dq": 1, "cs_n": 1, "clk": 0})