update test

diff --git a/src/nmutil/test/test_buf_pipe.py b/src/nmutil/test/test_buf_pipe.py
index 9035d932124d855066ba24bf42a86b3374cb3651..e27f382b9f6d53bfdbd9b1e3d7a44c60d55c5b17 100644 (file)
--- a/src/nmutil/test/test_buf_pipe.py
+++ b/src/nmutil/test/test_buf_pipe.py
@@ -19,13 +19,15 @@ from nmigen.hdl.rec import Record
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from .example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
-from .example_buf_pipe import ExamplePipeline, UnbufferedPipeline
-from .example_buf_pipe import ExampleStageCls
-from .example_buf_pipe import PrevControl, NextControl, BufferedHandshake
-from .example_buf_pipe import StageChain, ControlBase, StageCls
+from nmutil.test.example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
+from nmutil.test.example_buf_pipe import ExamplePipeline, UnbufferedPipeline
+from nmutil.test.example_buf_pipe import ExampleStageCls
+from nmutil.iocontrol import PrevControl, NextControl
+from nmutil.stageapi import StageChain, StageCls
+from nmutil.singlepipe import ControlBase
 from nmutil.singlepipe import UnbufferedPipeline2
 from nmutil.singlepipe import SimpleHandshake
+from nmutil.singlepipe import BufferedHandshake
 from nmutil.singlepipe import PassThroughHandshake
 from nmutil.singlepipe import PassThroughStage
 from nmutil.singlepipe import FIFOControl