Add internal op field to major decoder

diff --git a/src/decoder/decoder.py b/src/decoder/decoder.py
index 65aa3338ed69c16da5b91c0445e9c72b94f63042..6aa96d61f5d4adf3ccf677f59c1ef11d4064f315 100644 (file)
--- a/src/decoder/decoder.py
+++ b/src/decoder/decoder.py
@@ -3,10 +3,26 @@ import csv
 import os
 from enum import Enum, unique
 
+@unique
 class Function(Enum):
     ALU = 0
     LDST = 1
 
+@unique
+class InternalOp(Enum):
+    OP_ADD = 0
+    OP_AND = 1
+    OP_B = 2
+    OP_BC = 3
+    OP_CMP = 4
+    OP_LOAD = 5
+    OP_MUL_L64 = 6
+    OP_OR = 7
+    OP_RLC = 8
+    OP_STORE = 9
+    OP_TDI = 10
+    OP_XOR = 11
+
 def get_csv(name):
     file_dir = os.path.dirname(os.path.realpath(__file__))
     with open(os.path.join(file_dir, name)) as csvfile:
@@ -20,6 +36,7 @@ class PowerDecoder(Elaboratable):
         self.opcode_in = Signal(6, reset_less=True)
 
         self.function_unit = Signal(Function, reset_less=True)
+        self.internal_op = Signal(InternalOp, reset_less=True)
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
@@ -29,6 +46,7 @@ class PowerDecoder(Elaboratable):
                 opcode = int(row['opcode'])
                 with m.Case(opcode):
                     comb += self.function_unit.eq(Function[row['unit']])
+                    comb += self.internal_op.eq(InternalOp[row['internal op']])
         return m
 
 

diff --git a/src/decoder/test/test_decoder.py b/src/decoder/test/test_decoder.py
index 37faddd1d64f2eae354fdb4f996590b513845ccb..222dedab1dd349d99c6044d05663efa647db2bda 100644 (file)
--- a/src/decoder/test/test_decoder.py
+++ b/src/decoder/test/test_decoder.py
@@ -5,7 +5,7 @@ from nmigen.cli import rtlil
 import sys
 import unittest
 sys.path.append("../")
-from decoder import PowerDecoder, Function, major_opcodes
+from decoder import PowerDecoder, Function, InternalOp, major_opcodes
 
 class DecoderTestCase(FHDLTestCase):
     def test_function_unit(self):
@@ -13,10 +13,12 @@ class DecoderTestCase(FHDLTestCase):
         comb = m.d.comb
         opcode = Signal(6)
         function_unit = Signal(Function)
+        internal_op = Signal(InternalOp)
 
         m.submodules.dut = dut = PowerDecoder()
         comb += [dut.opcode_in.eq(opcode),
-                 function_unit.eq(dut.function_unit)]
+                 function_unit.eq(dut.function_unit),
+                 internal_op.eq(dut.internal_op)]
 
         sim = Simulator(m)
         def process():
@@ -26,8 +28,12 @@ class DecoderTestCase(FHDLTestCase):
                 result = yield function_unit
                 expected = Function[row['unit']].value
                 self.assertEqual(expected, result)
+
+                result = yield internal_op
+                expected = InternalOp[row['internal op']].value
+                self.assertEqual(expected, result)
         sim.add_process(process)
-        with sim.write_vcd("test.vcd", "test.gtkw", traces=[opcode, function_unit]):
+        with sim.write_vcd("test.vcd", "test.gtkw", traces=[opcode, function_unit, internal_op]):
             sim.run()
 
     def test_ilang(self):