add debug start/stop to firmware_upload script

diff --git a/src/soc/debug/firmware_upload.py b/src/soc/debug/firmware_upload.py
index 3b41654fdf7915197c47ac9e70534c8107f30abe..e388243e933c08aaad6d25485bc11321dec95c36 100644 (file)
--- a/src/soc/debug/firmware_upload.py
+++ b/src/soc/debug/firmware_upload.py
@@ -40,14 +40,14 @@ WB_READ = 6
 WB_WRRD = 7
 
 
-def read_dmi_addr(dmi_addr):
+def read_dmi_addr(dut, dmi_addr):
     # write DMI address
     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, dmi_addr)
 
     # read DMI register
     return (yield from jtag_read_write_reg(dut, DMI_READ, 64))
 
-def writeread_dmi_addr(dmi_addr, data):
+def writeread_dmi_addr(dut, dmi_addr, data):
     # write DMI address
     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, dmi_addr)
 
@@ -76,13 +76,13 @@ def jtag_sim(dut, firmware):
 
     ####### JTAG to DMI Setup (stop, reset) ######
 
-    yield from read_dmi_addr(dut, DMI_ADDR, 8, DBGCore.CTRL)
+    yield from read_dmi_addr(dut, DBGCore.CTRL)
     # read DMI CTRL reg
     status = yield from read_dmi_addr(dut, DBGCore.CTRL)
     print ("dmi ctrl status", bin(status))
 
     # write DMI CTRL register - STOP and RESET
-    status = yield from writeread_dmi_addr(dut, DBCCore.CTRL, 0b011)
+    status = yield from writeread_dmi_addr(dut, DBGCore.CTRL, 0b011)
     print ("dmi ctrl status", hex(status))
     assert status == 4 # returned old value (nice! cool feature!)
 
@@ -90,7 +90,7 @@ def jtag_sim(dut, firmware):
     while True:
         status = yield from read_dmi_addr(dut, DBGCore.STAT)
         print ("dmi ctrl status", bin(status))
-        if status & DBGStat.STOPPED:
+        if (status & (1<<DBGStat.STOPPED)) or (status & (1<<DBGStat.TERM)):
             break
 
     ####### JTAG to Wishbone ######
@@ -114,17 +114,19 @@ def jtag_sim(dut, firmware):
     ####### JTAG to DMI Setup (IC-Reset, start) ######
 
     # write DMI CTRL register - ICRESET
-    status = yield from writeread_dmi_addr(dut, DBCCore.CTRL, DBGCtrl.ICRESET)
+    status = yield from writeread_dmi_addr(dut, DBGCore.CTRL,
+                                           1<<DBGCtrl.ICRESET)
     print ("dmi ctrl status", hex(status))
 
     # write DMI CTRL register - START
-    status = yield from writeread_dmi_addr(dut, DBCCore.CTRL, DBGCtrl.START)
+    status = yield from writeread_dmi_addr(dut, DBGCore.CTRL,
+                                           1<<DBGCtrl.START)
     print ("dmi ctrl status", hex(status))
 
     # read STAT just for info
     for i in range(4):
         status = yield from read_dmi_addr(dut, DBGCore.STAT)
-        print ("dmi ctrl status", bin(status))
+        print ("dmi stat status", bin(status))
 
     ####### done - tell dmi_sim to stop (otherwise it won't) ########
 

diff --git a/src/soc/debug/test/dmi_sim.py b/src/soc/debug/test/dmi_sim.py
index 66d544d1993e95739d416edc7a7fbbbae003b224..aa6760f484ee06dff9bd8b8a6b6b46a0c0353c2a 100644 (file)
--- a/src/soc/debug/test/dmi_sim.py
+++ b/src/soc/debug/test/dmi_sim.py
@@ -1,7 +1,7 @@
 """DMI "simulator" process for nmigen tests
 """
 
-from soc.debug.dmi import  DBGCore
+from soc.debug.dmi import  DBGCore, DBGCtrl, DBGStat
 
 def dmi_sim(dut):
 
@@ -19,18 +19,29 @@ def dmi_sim(dut):
         wen = yield dmi.we_i
         addr = yield dmi.addr_i
         print ("        dmi wen, addr", wen, addr)
+
+        # Control read
         if addr == DBGCore.CTRL and wen == 0:
             print ("        read ctrl reg", ctrl_reg)
             yield dmi.dout.eq(ctrl_reg)
             yield dmi.ack_o.eq(1)
             yield
             yield dmi.ack_o.eq(0)
+
+        # Control write
         elif addr == DBGCore.CTRL and wen == 1:
-            ctrl_reg = (yield dmi.din)
-            print ("        write ctrl reg", ctrl_reg)
+            stat = (yield dmi.din)
+            if (stat & (1<<DBGCtrl.STOP)):
+                ctrl_reg |= (1<<DBGStat.STOPPED)
+                ctrl_reg &= ~(1<<DBGStat.STOPPING)
+            if (stat & (1<<DBGCtrl.START)):
+                ctrl_reg = 0
+            print ("        write ctrl reg", stat, ctrl_reg)
             yield dmi.ack_o.eq(1)
             yield
             yield dmi.ack_o.eq(0)
+
+        # allow MSR write
         elif addr == DBGCore.MSR and wen == 0:
             print ("        read msr reg")
             yield dmi.dout.eq(0xdeadbeef) # test MSR value

diff --git a/src/soc/debug/test/test_jtag_tap.py b/src/soc/debug/test/test_jtag_tap.py
index 6cc7e14c97aeeb9b65aee8c0f126abafe2795308..757c313c54a67db054097cc8dba979cac64424b1 100644 (file)
--- a/src/soc/debug/test/test_jtag_tap.py
+++ b/src/soc/debug/test/test_jtag_tap.py
@@ -115,7 +115,7 @@ def jtag_sim(dut):
     # read DMI CTRL register
     status = yield from jtag_read_write_reg(dut, DMI_READ, 64)
     print ("dmi ctrl status", hex(status))
-    assert status == 5
+    assert status == 0
 
     # write DMI MSR address
     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.MSR)

diff --git a/src/soc/debug/test/test_jtag_tap_srv.py b/src/soc/debug/test/test_jtag_tap_srv.py
index 25e2cdd457282b641eed6c18fb31040afb384aa0..ff3d330c271ba38af873ea51f82024467988c2d5 100644 (file)
--- a/src/soc/debug/test/test_jtag_tap_srv.py
+++ b/src/soc/debug/test/test_jtag_tap_srv.py
@@ -156,7 +156,7 @@ def jtag_sim(dut, srv_dut):
     # read DMI CTRL register
     status = yield from jtag_read_write_reg(dut, DMI_READ, 64)
     print ("dmi ctrl status", hex(status))
-    assert status == 5
+    assert status == 0
 
     # write DMI MSR address
     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.MSR)