fn_issue_l.append(fu.issue_i)
fn_busy_l.append(fu.busy_o)
# XXX sync, so as to stop a simulation infinite loop
- m.d.sync += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
- m.d.sync += fu.dest_i.eq(issueunit.i.dest_i)
- m.d.sync += fu.src1_i.eq(issueunit.i.src1_i)
- m.d.sync += fu.src2_i.eq(issueunit.i.src2_i)
- m.d.sync += issueunit.i.busy_i[i].eq(fu.busy_o)
+ m.d.comb += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
+ m.d.comb += fu.dest_i.eq(issueunit.i.dest_i)
+ m.d.comb += fu.src1_i.eq(issueunit.i.src1_i)
+ m.d.comb += fu.src2_i.eq(issueunit.i.src2_i)
+ m.d.comb += issueunit.i.busy_i[i].eq(fu.busy_o)
#---------
# connect Function Units
def elaborate(self, platform):
m = Module()
m.submodules.rd_l = rd_l = SRLatch(sync=False)
- m.submodules.wr_l = wr_l = SRLatch(sync=False)
+ m.submodules.wr_l = wr_l = SRLatch(sync=True)
m.submodules.dest_d = dest_d = Decoder(self.reg_width)
m.submodules.src1_d = src1_d = Decoder(self.reg_width)
m.submodules.src2_d = src2_d = Decoder(self.reg_width)
Pending. Can be used for INT or FP Global Pending.
Inputs:
- * :wid: register file width
+ * :dep: register file depth
* :fu_vecs: a python list of function unit "pending" vectors, each
vector being a Signal of width equal to the reg file.
on a particular register (extremely unusual), they must set a Const
zero bit in the vector.
"""
- def __init__(self, wid, fu_vecs):
- self.reg_width = wid
+ def __init__(self, dep, fu_vecs):
+ self.reg_dep = dep
# inputs
self.fu_vecs = fu_vecs
for v in fu_vecs:
- assert len(v) == wid, "FU Vector must be same width as regfile"
+ assert len(v) == dep, "FU Vector must be same width as regfile"
self.g_pend_o = Signal(wid, reset_less=True) # global pending vector