add JTAG enable/disable of 4k SRAMs

diff --git a/src/soc/bus/SPBlock512W64B8W.py b/src/soc/bus/SPBlock512W64B8W.py
index bb15de29caf3c95b8531dd5275cfab7f84515bfb..264578be629fc4b55ee4da88e3c29be95f222f3b 100644 (file)
--- a/src/soc/bus/SPBlock512W64B8W.py
+++ b/src/soc/bus/SPBlock512W64B8W.py
@@ -13,6 +13,7 @@ class SPBlock512W64B8W(Elaboratable):
     """
 
     def __init__(self, bus=None, features=None, name=None):
+        self.enable = Signal(reset=1) # enable signal, defaults to 1
         if features is None:
             features = frozenset()
         if bus is None:
@@ -48,25 +49,26 @@ class SPBlock512W64B8W(Elaboratable):
         m.submodules += sram
         sram.attrs['blackbox'] = 1
 
-        # wishbone is active if cyc and stb set
-        wb_active = Signal()
-        m.d.comb += wb_active.eq(self.bus.cyc & self.bus.stb)
+        with m.If(self.enable): # in case of layout problems
+            # wishbone is active if cyc and stb set
+            wb_active = Signal()
+            m.d.comb += wb_active.eq(self.bus.cyc & self.bus.stb)
 
-        # generate ack (no "pipeline" mode here)
-        m.d.sync += self.bus.ack.eq(wb_active)
+            # generate ack (no "pipeline" mode here)
+            m.d.sync += self.bus.ack.eq(wb_active)
 
-        with m.If(wb_active):
+            with m.If(wb_active):
 
-            # address
-            m.d.comb += a.eq(self.bus.adr)
+                # address
+                m.d.comb += a.eq(self.bus.adr)
 
-            # read 
-            m.d.comb += self.bus.dat_r.eq(q)
+                # read
+                m.d.comb += self.bus.dat_r.eq(q)
 
-            # write
-            m.d.comb += d.eq(self.bus.dat_w)
-            with m.If(self.bus.we):
-                m.d.comb += we.eq(self.bus.sel)
+                # write
+                m.d.comb += d.eq(self.bus.dat_w)
+                with m.If(self.bus.we):
+                    m.d.comb += we.eq(self.bus.sel)
 
         return m
 

diff --git a/src/soc/debug/jtag.py b/src/soc/debug/jtag.py
index 1f5508c52e2a988405e51f3e388500f683d79326..5cac2cd44c8868efbaa0ac4e0148a9f6a5d11be2 100644 (file)
--- a/src/soc/debug/jtag.py
+++ b/src/soc/debug/jtag.py
@@ -87,18 +87,22 @@ class JTAG(DMITAP, Pins):
         # create DMI2JTAG (goes through to dmi_sim())
         self.dmi = self.add_dmi(ircodes=[8, 9, 10])
 
-        # use this for enable/disable of parts of the ASIC
-        self.sr_en = self.add_shiftreg(ircode=11, length=2)
+        # use this for enable/disable of parts of the ASIC.
+        # NOTE: increase length parameter when adding new enable signals
+        self.sr_en = self.add_shiftreg(ircode=11, length=3)
         self.wb_icache_en = Signal(reset=1)
         self.wb_dcache_en = Signal(reset=1)
+        self.wb_sram_en = Signal(reset=1)
 
     def elaborate(self, platform):
         m = super().elaborate(platform)
         m.d.comb += self.sr.i.eq(self.sr.o) # loopback as part of test?
 
-        # provide way to enable/disable wishbone caches just in case of issues
+        # provide way to enable/disable wishbone caches and SRAM
+        # just in case of issues
         # see https://bugs.libre-soc.org/show_bug.cgi?id=520
-        en_sigs = Cat(self.wb_icache_en, self.wb_dcache_en)
+        en_sigs = Cat(self.wb_icache_en, self.wb_dcache_en,
+                      self.wb_sram_en)
         with m.If(self.sr_en.oe):
             m.d.sync += en_sigs.eq(self.sr_en.o)
         # also make it possible to read the enable/disable current state

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index ceec6f352452982bdb64cd33f437cd12a73d020d..cb6a3bfe09e8ed3863ed28bfa93bad8c3fc0c18c 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -16,7 +16,7 @@ improved.
 """
 
 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
-                    ClockDomain, DomainRenamer, Mux)
+                    ClockDomain, DomainRenamer, Mux, Const)
 from nmigen.cli import rtlil
 from nmigen.cli import main
 import sys
@@ -75,9 +75,12 @@ class TestIssuerInternal(Elaboratable):
             # honestly probably not.
             pspec.wb_icache_en = self.jtag.wb_icache_en
             pspec.wb_dcache_en = self.jtag.wb_dcache_en
+            self.wb_sram_en = self.jtag.wb_sram_en
+        else:
+            self.wb_sram_en = Const(1)
 
         # add 4k sram blocks?
-        self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and 
+        self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
                          pspec.sram4x4kblock == True)
         if self.sram4x4k:
             self.sram4k = []
@@ -162,6 +165,7 @@ class TestIssuerInternal(Elaboratable):
         if self.sram4x4k:
             for i, sram in enumerate(self.sram4k):
                 m.submodules["sram4k_%d" % i] = sram
+                comb += sram.enable.eq(self.wb_sram_en)
 
         # XICS interrupt handler
         if self.xics:

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index ebe93b4b960d8b101c89497cb44705983c29a5fc..79c9619e9e15d91e48dc12297f96ff66528d9b6f 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -28,14 +28,14 @@ if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
     # suite.addTest(TestRunner(HelloTestCases.test_data))
-    suite.addTest(TestRunner(DivTestCases().test_data))
+    #suite.addTest(TestRunner(DivTestCases().test_data))
     # suite.addTest(TestRunner(AttnTestCase.test_data))
-    suite.addTest(TestRunner(GeneralTestCases.test_data))
-    suite.addTest(TestRunner(LDSTTestCase().test_data))
-    suite.addTest(TestRunner(CRTestCase().test_data))
-    suite.addTest(TestRunner(ShiftRotTestCase().test_data))
+    #suite.addTest(TestRunner(GeneralTestCases.test_data))
+    #suite.addTest(TestRunner(LDSTTestCase().test_data))
+    #suite.addTest(TestRunner(CRTestCase().test_data))
+    #suite.addTest(TestRunner(ShiftRotTestCase().test_data))
     suite.addTest(TestRunner(LogicalTestCase().test_data))
-    suite.addTest(TestRunner(ALUTestCase().test_data))
+    #suite.addTest(TestRunner(ALUTestCase().test_data))
     # suite.addTest(TestRunner(BranchTestCase.test_data))
     # suite.addTest(TestRunner(SPRTestCase.test_data))