--- /dev/null
+# IEEE Floating Point Adder (Single Precision)
+# Copyright (C) Jonathan P Dawson 2013
+# 2013-12-12
+
+from nmigen import Module, Signal, Cat
+from nmigen.cli import main, verilog
+
+from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
+
+
+class FPADD(FPBase):
+
+ def __init__(self, width, single_cycle=False):
+ FPBase.__init__(self)
+ self.width = width
+ self.single_cycle = single_cycle
+
+ self.in_a = FPOp(width)
+ self.in_b = FPOp(width)
+ self.out_z = FPOp(width)
+
+ def get_fragment(self, platform=None):
+ """ creates the HDL code-fragment for FPAdd
+ """
+ m = Module()
+
+ # Latches
+ a = FPNumIn(self.in_a, self.width)
+ b = FPNumIn(self.in_b, self.width)
+ z = FPNumOut(self.width, False)
+
+ m.submodules.fpnum_a = a
+ m.submodules.fpnum_b = b
+ m.submodules.fpnum_z = z
+
+ m.d.comb += a.v.eq(self.in_a.v)
+ m.d.comb += b.v.eq(self.in_b.v)
+
+ w = z.m_width + 4
+ tot = Signal(w, reset_less=True) # sticky/round/guard, {mantissa} result, 1 overflow
+
+ of = Overflow()
+
+ m.submodules.overflow = of
+
+ with m.FSM() as fsm:
+
+ # ******
+ # gets operand a
+
+ with m.State("get_a"):
+ self.get_op(m, self.in_a, a, "get_b")
+
+ # ******
+ # gets operand b
+
+ with m.State("get_b"):
+ self.get_op(m, self.in_b, b, "special_cases")
+
+ # ******
+ # special cases: NaNs, infs, zeros, denormalised
+ # NOTE: some of these are unique to add. see "Special Operations"
+ # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
+
+ with m.State("special_cases"):
+
+ s_nomatch = Signal()
+ m.d.comb += s_nomatch.eq(a.s != b.s)
+
+ m_match = Signal()
+ m.d.comb += m_match.eq(a.m == b.m)
+
+ # if a is NaN or b is NaN return NaN
+ with m.If(a.is_nan | b.is_nan):
+ m.next = "put_z"
+ m.d.sync += z.nan(1)
+
+ # XXX WEIRDNESS for FP16 non-canonical NaN handling
+ # under review
+
+ ## if a is zero and b is NaN return -b
+ #with m.If(a.is_zero & (a.s==0) & b.is_nan):
+ # m.next = "put_z"
+ # m.d.sync += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
+
+ ## if b is zero and a is NaN return -a
+ #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
+ # m.next = "put_z"
+ # m.d.sync += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
+
+ ## if a is -zero and b is NaN return -b
+ #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
+ # m.next = "put_z"
+ # m.d.sync += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
+
+ ## if b is -zero and a is NaN return -a
+ #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
+ # m.next = "put_z"
+ # m.d.sync += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
+
+ # if a is inf return inf (or NaN)
+ with m.Elif(a.is_inf):
+ m.next = "put_z"
+ m.d.sync += z.inf(a.s)
+ # if a is inf and signs don't match return NaN
+ with m.If(b.exp_128 & s_nomatch):
+ m.d.sync += z.nan(1)
+
+ # if b is inf return inf
+ with m.Elif(b.is_inf):
+ m.next = "put_z"
+ m.d.sync += z.inf(b.s)
+
+ # if a is zero and b zero return signed-a/b
+ with m.Elif(a.is_zero & b.is_zero):
+ m.next = "put_z"
+ m.d.sync += z.create(a.s & b.s, b.e, b.m[3:-1])
+
+ # if a is zero return b
+ with m.Elif(a.is_zero):
+ m.next = "put_z"
+ m.d.sync += z.create(b.s, b.e, b.m[3:-1])
+
+ # if b is zero return a
+ with m.Elif(b.is_zero):
+ m.next = "put_z"
+ m.d.sync += z.create(a.s, a.e, a.m[3:-1])
+
+ # if a equal to -b return zero (+ve zero)
+ with m.Elif(s_nomatch & m_match & (a.e == b.e)):
+ m.next = "put_z"
+ m.d.sync += z.zero(0)
+
+ # Denormalised Number checks
+ with m.Else():
+ m.next = "align"
+ self.denormalise(m, a)
+ self.denormalise(m, b)
+
+ # ******
+ # align.
+
+ with m.State("align"):
+ if not self.single_cycle:
+ # NOTE: this does *not* do single-cycle multi-shifting,
+ # it *STAYS* in the align state until exponents match
+
+ # exponent of a greater than b: shift b down
+ with m.If(a.e > b.e):
+ m.d.sync += b.shift_down()
+ # exponent of b greater than a: shift a down
+ with m.Elif(a.e < b.e):
+ m.d.sync += a.shift_down()
+ # exponents equal: move to next stage.
+ with m.Else():
+ m.next = "add_0"
+ else:
+ # This one however (single-cycle) will do the shift
+ # in one go.
+
+ # XXX TODO: the shifter used here is quite expensive
+ # having only one would be better
+
+ ediff = Signal((len(a.e), True), reset_less=True)
+ ediffr = Signal((len(a.e), True), reset_less=True)
+ m.d.comb += ediff.eq(a.e - b.e)
+ m.d.comb += ediffr.eq(b.e - a.e)
+ with m.If(ediff > 0):
+ m.d.sync += b.shift_down_multi(ediff)
+ # exponent of b greater than a: shift a down
+ with m.Elif(ediff < 0):
+ m.d.sync += a.shift_down_multi(ediffr)
+
+ m.next = "add_0"
+
+ # ******
+ # First stage of add. covers same-sign (add) and subtract
+ # special-casing when mantissas are greater or equal, to
+ # give greatest accuracy.
+
+ with m.State("add_0"):
+ m.next = "add_1"
+ m.d.sync += z.e.eq(a.e)
+ # same-sign (both negative or both positive) add mantissas
+ with m.If(a.s == b.s):
+ m.d.sync += [
+ tot.eq(Cat(a.m, 0) + Cat(b.m, 0)),
+ z.s.eq(a.s)
+ ]
+ # a mantissa greater than b, use a
+ with m.Elif(a.m >= b.m):
+ m.d.sync += [
+ tot.eq(Cat(a.m, 0) - Cat(b.m, 0)),
+ z.s.eq(a.s)
+ ]
+ # b mantissa greater than a, use b
+ with m.Else():
+ m.d.sync += [
+ tot.eq(Cat(b.m, 0) - Cat(a.m, 0)),
+ z.s.eq(b.s)
+ ]
+
+ # ******
+ # Second stage of add: preparation for normalisation.
+ # detects when tot sum is too big (tot[27] is kinda a carry bit)
+
+ with m.State("add_1"):
+ m.next = "normalise_1"
+ # tot[27] gets set when the sum overflows. shift result down
+ with m.If(tot[-1]):
+ m.d.sync += [
+ z.m.eq(tot[4:]),
+ of.m0.eq(tot[4]),
+ of.guard.eq(tot[3]),
+ of.round_bit.eq(tot[2]),
+ of.sticky.eq(tot[1] | tot[0]),
+ z.e.eq(z.e + 1)
+ ]
+ # tot[27] zero case
+ with m.Else():
+ m.d.sync += [
+ z.m.eq(tot[3:]),
+ of.m0.eq(tot[3]),
+ of.guard.eq(tot[2]),
+ of.round_bit.eq(tot[1]),
+ of.sticky.eq(tot[0])
+ ]
+
+ # ******
+ # First stage of normalisation.
+
+ with m.State("normalise_1"):
+ self.normalise_1(m, z, of, "normalise_2")
+
+ # ******
+ # Second stage of normalisation.
+
+ with m.State("normalise_2"):
+ self.normalise_2(m, z, of, "round")
+
+ # ******
+ # rounding stage
+
+ with m.State("round"):
+ self.roundz(m, z, of.roundz)
+ m.next = "corrections"
+
+ # ******
+ # correction stage
+
+ with m.State("corrections"):
+ self.corrections(m, z, "pack")
+
+ # ******
+ # pack stage
+
+ with m.State("pack"):
+ self.pack(m, z, "put_z")
+
+ # ******
+ # put_z stage
+
+ with m.State("put_z"):
+ self.put_z(m, z, self.out_z, "get_a")
+
+ return m
+
+
+if __name__ == "__main__":
+ alu = FPADD(width=32)
+ main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
+
+
+ # works... but don't use, just do "python fname.py convert -t v"
+ #print (verilog.convert(alu, ports=[
+ # ports=alu.in_a.ports() + \
+ # alu.in_b.ports() + \
+ # alu.out_z.ports())
--- /dev/null
+from random import randint
+from random import seed
+from operator import add
+
+from nmigen import Module, Signal
+from nmigen.compat.sim import run_simulation
+
+from fadd_state import FPADD
+
+from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
+ is_inf, is_pos_inf, is_neg_inf,
+ match, get_case, check_case, run_test,
+ run_edge_cases, run_corner_cases)
+
+def testbench(dut):
+ yield from check_case(dut, 0xFFFFFFFF, 0xC63B800A, 0xFFC00000)
+ yield from check_case(dut, 0xFF800000, 0x7F800000, 0xFFC00000)
+ #yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
+ yield from check_case(dut, 0x7F800000, 0xFF800000, 0xFFC00000)
+ yield from check_case(dut, 0x42540000, 0xC2540000, 0x00000000)
+ yield from check_case(dut, 0xC2540000, 0x42540000, 0x00000000)
+ yield from check_case(dut, 0xfe34f995, 0xff5d59ad, 0xff800000)
+ yield from check_case(dut, 0x82471f51, 0x243985f, 0x801c3790)
+ yield from check_case(dut, 0, 0, 0)
+ yield from check_case(dut, 0x40000000, 0xc0000000, 0x00000000)
+ yield from check_case(dut, 0x3F800000, 0x40000000, 0x40400000)
+ yield from check_case(dut, 0x40000000, 0x3F800000, 0x40400000)
+ yield from check_case(dut, 0x447A0000, 0x4488B000, 0x4502D800)
+ yield from check_case(dut, 0x463B800A, 0x42BA8A3D, 0x463CF51E)
+ yield from check_case(dut, 0x42BA8A3D, 0x463B800A, 0x463CF51E)
+ yield from check_case(dut, 0x463B800A, 0xC2BA8A3D, 0x463A0AF6)
+ yield from check_case(dut, 0xC2BA8A3D, 0x463B800A, 0x463A0AF6)
+ yield from check_case(dut, 0xC63B800A, 0x42BA8A3D, 0xC63A0AF6)
+ yield from check_case(dut, 0x42BA8A3D, 0xC63B800A, 0xC63A0AF6)
+ yield from check_case(dut, 0x7F800000, 0x00000000, 0x7F800000)
+ yield from check_case(dut, 0x00000000, 0x7F800000, 0x7F800000)
+ yield from check_case(dut, 0xFF800000, 0x00000000, 0xFF800000)
+ yield from check_case(dut, 0x00000000, 0xFF800000, 0xFF800000)
+ yield from check_case(dut, 0x7F800000, 0x7F800000, 0x7F800000)
+ yield from check_case(dut, 0xFF800000, 0xFF800000, 0xFF800000)
+ yield from check_case(dut, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
+ yield from check_case(dut, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
+ yield from check_case(dut, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)
+ yield from check_case(dut, 0x7EFFFFEE, 0x7EFFFFEE, 0x7F7FFFEE)
+ yield from check_case(dut, 0x7F7FFFEE, 0xFEFFFFEE, 0x7EFFFFEE)
+ yield from check_case(dut, 0x7F7FFFEE, 0x756CA884, 0x7F7FFFFD)
+ yield from check_case(dut, 0x7F7FFFEE, 0x758A0CF8, 0x7F7FFFFF)
+ yield from check_case(dut, 0x42500000, 0x51A7A358, 0x51A7A358)
+ yield from check_case(dut, 0x51A7A358, 0x42500000, 0x51A7A358)
+ yield from check_case(dut, 0x4E5693A4, 0x42500000, 0x4E5693A5)
+ yield from check_case(dut, 0x42500000, 0x4E5693A4, 0x4E5693A5)
+ #yield from check_case(dut, 1, 0, 1)
+ #yield from check_case(dut, 1, 1, 1)
+
+ count = 0
+
+ #regression tests
+ stimulus_a = [0x22cb525a, 0x40000000, 0x83e73d5c, 0xbf9b1e94, 0x34082401,
+ 0x5e8ef81, 0x5c75da81, 0x2b017]
+ stimulus_b = [0xadd79efa, 0xC0000000, 0x1c800000, 0xc038ed3a, 0xb328cd45,
+ 0x114f3db, 0x2f642a39, 0xff3807ab]
+ yield from run_test(dut, stimulus_a, stimulus_b, add, check_case)
+ count += len(stimulus_a)
+ print (count, "vectors passed")
+
+ yield from run_corner_cases(dut, count, add)
+ yield from run_edge_cases(dut, count, add)
+
+if __name__ == '__main__':
+ dut = FPADD(width=32, single_cycle=True)
+ run_simulation(dut, testbench(dut), vcd_name="test_state_add.vcd")
+
projects / ieee754fpu.git / commitdiff