add debug info, update comments, disable dcache in test

all tracking down bugs in test_ldst_pi.py

diff --git a/src/soc/experiment/test/test_ldst_pi.py b/src/soc/experiment/test/test_ldst_pi.py
index 82f56482f93a7cbd4673bde542bf6d0e1964cbff..cd9a6773db6c8bf1a928544ccbc355de269f8148 100644 (file)
--- a/src/soc/experiment/test/test_ldst_pi.py
+++ b/src/soc/experiment/test/test_ldst_pi.py
@@ -138,6 +138,7 @@ def test_mmu():
 
     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
                          imem_ifacetype='',
+                         disable_cache=True,
                          addr_wid=48,
                          mask_wid=8,
                          reg_wid=64)

diff --git a/src/soc/experiment/test/test_mmu_dcache_pi.py b/src/soc/experiment/test/test_mmu_dcache_pi.py
index a19d9cc5aec1a61b42a02774c979925e4342c457..35d5808118d919be76e39f5f6f69ca1a321704a0 100644 (file)
--- a/src/soc/experiment/test/test_mmu_dcache_pi.py
+++ b/src/soc/experiment/test/test_mmu_dcache_pi.py
@@ -1,7 +1,7 @@
 """MMU PortInterface Test
 
-quite basic, goes directly to the MMU to assert signals (does not
-yet use PortInterface)
+quite basic, calls pi_ld to get data via PortInterface.  this test
+shouldn't really exist, it's superceded by test_ldst_pi.py
 """
 
 from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index e5815b16639d3d86e44be87f3a22201b06a9d931..23d8fa4faa5b64c6550bd5f6fad1b0bd8d08bc17 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -30,6 +30,7 @@ from soc.experiment.mem_types import MMUToLoadStore1Type
 
 from soc.minerva.wishbone import make_wb_layout
 from soc.bus.sram import SRAM
+from nmutil.util import Display
 
 
 @unique
@@ -212,11 +213,13 @@ class LoadStore1(PortInterfaceBase):
             with m.Case(State.MMU_LOOKUP):
                 with m.If(m_in.done):
                     with m.If(~self.instr_fault):
+                        sync += Display("MMU_LOOKUP, done %x", self.addr)
                         # retry the request now that the MMU has
                         # installed a TLB entry
                         m.d.comb += self.d_validblip.eq(1) # re-run dcache req
                         sync += self.state.eq(State.ACK_WAIT)
                     with m.Else():
+                        sync += Display("MMU_LOOKUP, exception %x", self.addr)
                         # instruction lookup fault: store address in DAR
                         comb += exc.happened.eq(1)
                         sync += self.dar.eq(self.addr)