put multi-ports back (for read) on int and fast regfiles

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 88b232096c5e96aba3bd190e4ba8f27814b6a691..58211449126b764cb14bb8c249bb05735f1fccd7 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -69,8 +69,9 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray):
         self.w_ports = {'o': self.write_port("dest1"),
                         #'o1': self.write_port("dest2") # for now (LD/ST update)
                         }
-        self.r_ports = {'rabc': self.read_port("src1"),
-                        #'rbc': self.read_port("src3"),
+        self.r_ports = {'ra': self.read_port("src1"),
+                        'rb': self.read_port("src2"),
+                        'rc': self.read_port("src3"),
                         'dmi': self.read_port("dmi")} # needed for Debug (DMI)
 
 
@@ -92,9 +93,10 @@ class FastRegs(RegFileMem): #RegFileArray):
     SRR1 = 4
     def __init__(self):
         super().__init__(64, 5)
-        self.w_ports = {'fast1': self.write_port("dest3"),
+        self.w_ports = {'fast1': self.write_port("dest1"),
                        }
         self.r_ports = {'fast1': self.read_port("src1"),
+                        'fast2': self.read_port("src2"),
                         }
 
 

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 117a937d325ee8fb37e1292d6c4be44e9c2454b9..e5b03ffcd2de3ad7b7f35fa3a1822b7ef93eb780 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -282,13 +282,14 @@ class NonProductionCore(Elaboratable):
 
             # argh.  an experiment to merge RA and RB in the INT regfile
             # (we have too many read/write ports)
-            if regfile == 'INT':
-                fuspecs['rabc'] = [fuspecs.pop('rb')]
-                fuspecs['rabc'].append(fuspecs.pop('rc'))
-                fuspecs['rabc'].append(fuspecs.pop('ra'))
-            if regfile == 'FAST':
-                fuspecs['fast1'] = [fuspecs.pop('fast1')]
-                fuspecs['fast1'].append(fuspecs.pop('fast2'))
+            #if regfile == 'INT':
+                #fuspecs['rabc'] = [fuspecs.pop('rb')]
+                #fuspecs['rabc'].append(fuspecs.pop('rc'))
+                #fuspecs['rabc'].append(fuspecs.pop('ra'))
+            #if regfile == 'FAST':
+            #    fuspecs['fast1'] = [fuspecs.pop('fast1')]
+            #    if 'fast2' in fuspecs:
+            #        fuspecs['fast1'].append(fuspecs.pop('fast2'))
 
             # for each named regfile port, connect up all FUs to that port
             for (regname, fspec) in sort_fuspecs(fuspecs):
@@ -412,7 +413,8 @@ class NonProductionCore(Elaboratable):
                 fuspecs['o'].append(fuspecs.pop('o1'))
             if regfile == 'FAST':
                 fuspecs['fast1'] = [fuspecs.pop('fast1')]
-                fuspecs['fast1'].append(fuspecs.pop('fast2'))
+                if 'fast2' in fuspecs:
+                    fuspecs['fast1'].append(fuspecs.pop('fast2'))
 
             for (regname, fspec) in sort_fuspecs(fuspecs):
                 self.connect_wrport(m, fu_bitdict, wrpickers,

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 90b8308131766e5f651ea321d948ef9992dbcee1..9ba52fe628d531f1170739caf464768827d45ac7 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -9,11 +9,14 @@ from soc.simple.issuer import TestIssuer
 
 
 if __name__ == '__main__':
-    units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
+    units = {'alu': 1,
+             'cr': 1, 'branch': 1, 'trap': 1,
+            'logical': 1,
              'spr': 1,
              'div': 1,
              'mul': 1,
-             'shiftrot': 1}
+             'shiftrot': 1
+                }
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
                          imem_ifacetype='bare_wb',
                          addr_wid=48,