if ck == PBase.get_clock_reset(self, name, count):
return ''
if ctype == 'slow':
- spc = "sp_clock, sp_reset"
+ spc = self.get_clk_spc(ctype)
else:
spc = ck
- ck = "core_clock, core_reset"
+ ck = self.get_clk_spc(ctype)
template = """\
Ifc_sync#({0}) {1}_sync <-mksyncconnection(
{2}, {3});"""
ret.append(template.format("Bit#(1)", n_, spc, ck))
return '\n'.join(ret)
+ def get_clk_spc(self, ctype):
+ if ctype == 'slow':
+ return "sp_clock, sp_reset"
+ else:
+ return "core_clock, core_reset"
+
def _mk_clk_vcon(self, name, count, ctype, typ, pname, bitspec):
ck = self.get_clock_reset(name, count)
if ck == PBase.get_clock_reset(self, name, count):
return ''
if ctype == 'slow':
- spc = "sp_clock, sp_reset"
+ spc = self.get_clk_spc(ctype)
else:
spc = ck
- ck = "core_clock, core_reset"
+ ck = self.get_clk_spc(ctype)
template = """\
Ifc_sync#({0}) {1}_sync <-mksyncconnection(
{2}, {3});"""
# YUK!
return "interface Ifc_jtagdtm jtag{0}_out;".format(count)
- def get_clock_reset(self, name, count):
+ def get_clk_spc(self, typ):
return "tck, trst"
+ def get_clock_reset(self, name, count):
+ return "slow_clock, slow_reset"
+
def pinname_in(self, pname):
return {'tms': 'tms',
'tdi': 'tdi',