naah. back to "sv." syntax for SVP64 assembly

diff --git a/src/soc/decoder/isa/test_caller_setvl.py b/src/soc/decoder/isa/test_caller_setvl.py
index cb21563542ee210c18b03adbc628c7575b7e4fd8..ad7991f18febae289809c53402f6d04841537fc6 100644 (file)
--- a/src/soc/decoder/isa/test_caller_setvl.py
+++ b/src/soc/decoder/isa/test_caller_setvl.py
@@ -49,7 +49,7 @@ class DecoderTestCase(FHDLTestCase):
         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
         isa = SVP64Asm(["setvl 3, 0, 1, 1, 1",
-                        'svadd 1.v, 5.v, 9.v'
+                        'sv.add 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)

diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py
index 44e71049fd94eb51d2606255de6edc82f4714a6d..7875dc089c638d717c5ea87c45288b837aaf4c93 100644 (file)
--- a/src/soc/decoder/isa/test_caller_svp64.py
+++ b/src/soc/decoder/isa/test_caller_svp64.py
@@ -26,8 +26,8 @@ class DecoderTestCase(FHDLTestCase):
                         "addi 2, 0, 0x0008",
                         "addi 5, 0, 0x1234",
                         "addi 6, 0, 0x1235",
-                        "svstw 5.v, 0(1.v)",
-                        "svlwz 9.v, 0(1.v)"])
+                        "sv.stw 5.v, 0(1.v)",
+                        "sv.lwz 9.v, 0(1.v)"])
         lst = list(lst)
 
         # SVSTATE (in this case, VL=2)
@@ -46,7 +46,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
-        isa = SVP64Asm(['svadd 1.v, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -75,7 +75,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
         #       r1 is scalar so ENDS EARLY
-        isa = SVP64Asm(['svadd 1, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -103,7 +103,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
         #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
-        isa = SVP64Asm(['svadd 1.v, 5, 9.v'
+        isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -131,7 +131,7 @@ class DecoderTestCase(FHDLTestCase):
     def test_sv_add_vl_0(self):
         # adds:
         #       none because VL is zer0
-        isa = SVP64Asm(['svadd 1, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -158,7 +158,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds when Rc=1:                               TODO CRs higher up
         #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
-        isa = SVP64Asm(['svadd. 1.v, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)

diff --git a/src/soc/decoder/isa/test_caller_svp64_predication.py b/src/soc/decoder/isa/test_caller_svp64_predication.py
index 999ee7029ca56ddc0022c52775eef994e476b198..837c42d89a5da871179b5ad1b92790f77dcc7371 100644 (file)
--- a/src/soc/decoder/isa/test_caller_svp64_predication.py
+++ b/src/soc/decoder/isa/test_caller_svp64_predication.py
@@ -26,8 +26,8 @@ class DecoderTestCase(FHDLTestCase):
                         "addi 2, 0, 0x0008",
                         "addi 5, 0, 0x1234",
                         "addi 6, 0, 0x1235",
-                        "svstw 5.v, 0(1.v)",
-                        "svlwz 9.v, 0(1.v)"])
+                        "sv.stw 5.v, 0(1.v)",
+                        "sv.lwz 9.v, 0(1.v)"])
         lst = list(lst)
 
         # SVSTATE (in this case, VL=2)
@@ -64,7 +64,7 @@ class DecoderTestCase(FHDLTestCase):
         #                              |
         #   dest r3=0b10             N Y
 
-        isa = SVP64Asm(['svextsb/sm=~r3/m=r3 5.v, 9.v'
+        isa = SVP64Asm(['sv.extsb/sm=~r3/m=r3 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -90,7 +90,7 @@ class DecoderTestCase(FHDLTestCase):
 
     def test_sv_extsw_intpred_dz(self):
         # extsb, integer twin-pred mask: dest is r3 (0b01), zeroing on dest
-        isa = SVP64Asm(['svextsb/m=r3/dz 5.v, 9.v'
+        isa = SVP64Asm(['sv.extsb/m=r3/dz 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -120,7 +120,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds, integer predicated mask r3=0b10
         #       1 = 5 + 9   => not to be touched (skipped)
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
-        isa = SVP64Asm(['svadd/m=r3 1.v, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add/m=r3 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -151,7 +151,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
         #       1 = 5 + 9   => not to be touched (skipped)
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
-        isa = SVP64Asm(['svadd/m=ne 1.v, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add/m=ne 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -185,7 +185,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
         #       r1 is scalar so ENDS EARLY
-        isa = SVP64Asm(['svadd 1, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -213,7 +213,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
         #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
-        isa = SVP64Asm(['svadd 1.v, 5, 9.v'
+        isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -241,7 +241,7 @@ class DecoderTestCase(FHDLTestCase):
     def tst_sv_add_vl_0(self):
         # adds:
         #       none because VL is zer0
-        isa = SVP64Asm(['svadd 1, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -268,7 +268,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds when Rc=1:                               TODO CRs higher up
         #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
-        isa = SVP64Asm(['svadd. 1.v, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)

diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
index 8320036dd91caa034fd4f99eb6b88d0239df8cd0..4ae5e8aeaae4c864e530f86ac742be3a1201dd47 100644 (file)
--- a/src/soc/fu/alu/test/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -11,7 +11,7 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
         #       2 = 6 + 10  => 0x3334 = 0x2223 + 0x1111
-        isa = SVP64Asm(['svadd 1.v, 5.v, 9.v'])
+        isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'])
         lst = list(isa)
         print("listing", lst)
 
@@ -33,7 +33,7 @@ class SVP64ALUTestCase(TestAccumulatorBase):
     def case_2_sv_add_scalar(self):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
-        isa = SVP64Asm(['svadd 1, 5, 9'])
+        isa = SVP64Asm(['sv.add 1, 5, 9'])
         lst = list(isa)
         print("listing", lst)
 
@@ -58,7 +58,7 @@ class SVP64ALUTestCase(TestAccumulatorBase):
     def case_3_sv_check_extra(self):
         # adds:
         #       13 = 10 + 7   => 0x4242 = 0x1230 + 0x3012
-        isa = SVP64Asm(['svadd 13.v, 10.v, 7.v'])
+        isa = SVP64Asm(['sv.add 13.v, 10.v, 7.v'])
         lst = list(isa)
         print("listing", lst)
 
@@ -80,7 +80,7 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
 
-        isa = SVP64Asm(['svadd. 1.v, 5.v, 9.v'])
+        isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'])
         lst = list(isa)
         print("listing", lst)
 
@@ -104,7 +104,7 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
         isa = SVP64Asm([
-            'svadd 13.v, 10.v, 7.v',  # skipped, because VL == 0
+            'sv.add 13.v, 10.v, 7.v',  # skipped, because VL == 0
             'add 1, 5, 9'
         ])
         lst = list(isa)
@@ -135,8 +135,8 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         #      14 = 11 + 8  => 0x3012 = 0x3012 + 0x0000
         #      15 = 12 + 9  => 0x1234 = 0x0000 + 0x1234
         isa = SVP64Asm([
-            'svadd 1.v, 5.v, 9.v',
-            'svadd 13.v, 10.v, 7.v'
+            'sv.add 1.v, 5.v, 9.v',
+            'sv.add 13.v, 10.v, 7.v'
         ])
         lst = list(isa)
         print("listing", lst)
@@ -162,7 +162,7 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
         #       r1 is scalar so ENDS EARLY
-        isa = SVP64Asm(['svadd 1, 5.v, 9.v'])
+        isa = SVP64Asm(['sv.add 1, 5.v, 9.v'])
         lst = list(isa)
         print("listing", lst)
 
@@ -184,7 +184,7 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
         #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
-        isa = SVP64Asm(['svadd 1.v, 5, 9.v'])
+        isa = SVP64Asm(['sv.add 1.v, 5, 9.v'])
         lst = list(isa)
         print("listing", lst)
 

diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index 18987e866ffb61b27bb721ca5f3e7f27d2c32a22..9001912461b8edfcd55ac0f080d21fc0189053bb 100644 (file)
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -180,10 +180,10 @@ class SVP64Asm:
                 continue
 
             # identify if is a svp64 mnemonic
-            if not opcode.startswith('sv'):
+            if not opcode.startswith('sv.'):
                 yield insn  # unaltered
                 continue
-            opcode = opcode[2:] # strip leading "sv"
+            opcode = opcode[3:] # strip leading "sv"
 
             # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
             opmodes = opcode.split("/") # split at "/"
@@ -617,21 +617,21 @@ class SVP64Asm:
 if __name__ == '__main__':
     lst = ['slw 3, 1, 4',
                  'extsw 5, 3',
-                 'svextsw 5, 3',
-                 'svcmpi 5, 1, 3, 2',
-                 'svsetb 5, 31',
-                 'svisel 64.v, 3, 2, 65.v',
-                 'svsetb/m=r3/sm=1<<r3 5, 31',
-                 'svsetb/vec2 5, 31',
-                 'svsetb/sw=8/ew=16 5, 31',
-                 'svextsw./ff=eq 5, 31',
-                 'svextsw./satu/sz/dz/sm=r3/m=r3 5, 31',
-                 'svextsw./pr=eq 5.v, 31',
-                 'svadd. 5.v, 2.v, 1.v',
+                 'sv.extsw 5, 3',
+                 'sv.cmpi 5, 1, 3, 2',
+                 'sv.setb 5, 31',
+                 'sv.isel 64.v, 3, 2, 65.v',
+                 'sv.setb/m=r3/sm=1<<r3 5, 31',
+                 'sv.setb/vec2 5, 31',
+                 'sv.setb/sw=8/ew=16 5, 31',
+                 'sv.extsw./ff=eq 5, 31',
+                 'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
+                 'sv.extsw./pr=eq 5.v, 31',
+                 'sv.add. 5.v, 2.v, 1.v',
                 ]
     lst += [
-                 'svstw 5.v, 4(1.v)',
-                 'svld 5.v, 4(1.v)',
+                 'sv.stw 5.v, 4(1.v)',
+                 'sv.ld 5.v, 4(1.v)',
                  'setvl. 2, 3, 4, 1, 1',
           ]
     isa = SVP64Asm(lst)