yield dut.int_store_i.eq(0)
- for i in range(100):
+ for i in range(500):
# set random values in the registers
for i in range(1, dut.n_regs):
# create some instructions (some random, some regression tests)
instrs = []
if True:
- for i in range(10):
+ for i in range(20):
src1 = randint(1, dut.n_regs-1)
src2 = randint(1, dut.n_regs-1)
while True:
writable.append(fu.writable_o)
# ... and output them from this module (horizontal, width=REGs)
- m.d.comb += self.readable_o.eq(Cat(*writable))
- m.d.comb += self.writable_o.eq(Cat(*readable))
+ m.d.comb += self.readable_o.eq(Cat(*readable))
+ m.d.comb += self.writable_o.eq(Cat(*writable))
# ---
# connect FU Pending
def elaborate(self, platform):
m = Module()
- m.d.comb += self.readable_o.eq(~self.rd_pend_i.bool())
- m.d.comb += self.writable_o.eq(~self.wr_pend_i.bool())
+
+ # Readable if there are no writes pending
+ m.d.comb += self.readable_o.eq(~self.wr_pend_i.bool())
+
+ # Writable if there are no reads pending
+ m.d.comb += self.writable_o.eq(~self.rd_pend_i.bool())
+
return m