comment tidyup

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index ab217bd0c0ddbbad495f86364d1d3cc2cf250daf..b2713639e1a15f841c869a7c629d6e72c40197fa 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -212,7 +212,7 @@ class LoadStore1(PortInterfaceBase):
                         m.d.comb += self.d_validblip.eq(1) # re-run dcache req
                         sync += self.state.eq(State.ACK_WAIT)
                     with m.Else():
-                        # instruction lookup fault:
+                        # instruction lookup fault: store address in DAR
                         comb += exc.happened.eq(1)
                         sync += self.dar.eq(self.addr)
 
@@ -228,6 +228,7 @@ class LoadStore1(PortInterfaceBase):
             with m.Case(State.TLBIE_WAIT):
                 pass
 
+        # alignment error: store address in DAR
         with m.If(self.align_intr):
             comb += exc.happened.eq(1)
             sync += self.dar.eq(self.addr)