Assert valid_o one clock early, as alu_done is asserted

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 007d8b69b297d192a1c35b07c1445b52d5167822..c2179cf95669d7ef46db136827af6b2372442a2d 100644 (file)
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -221,10 +221,10 @@ class ALU(Elaboratable):
         # in a sequential ALU, valid_o rises when the ALU is done
         # and falls when acknowledged by ready_i
         valid_o = Signal()
-        with m.If(alu_done):
-            m.d.sync += valid_o.eq(1)
-        with m.Elif(self.n.ready_i):
+        with m.If(self.n.ready_i):
             m.d.sync += valid_o.eq(0)
+        with m.Elif(alu_done):
+            m.d.sync += valid_o.eq(1)
 
         # select handshake handling according to ALU type
         with m.If(go_now):
@@ -237,7 +237,7 @@ class ALU(Elaboratable):
             # ready_o responds to valid_i, but only if the ALU is idle
             m.d.comb += self.p.ready_o.eq(self.p.valid_i & alu_idle)
             # select the internally generated valid_o, above
-            m.d.comb += self.n.valid_o.eq(valid_o)
+            m.d.comb += self.n.valid_o.eq(valid_o | alu_done)
 
         # hold the ALU result until ready_o is asserted
         alu_r = Signal(self.width)
@@ -262,9 +262,9 @@ class ALU(Elaboratable):
                 # SHIFT to take 7
                 with m.Elif(self.op.insn_type == InternalOp.OP_SHR):
                     m.d.sync += self.counter.eq(7)
-                # ADD/SUB to take 2, straight away
+                # ADD/SUB to take 1, straight away
                 with m.Elif(self.op.insn_type == InternalOp.OP_ADD):
-                    m.d.sync += self.counter.eq(3)
+                    m.d.sync += self.counter.eq(1)
                 # others to take no delay
                 with m.Else():
                     m.d.comb += go_now.eq(1)