core_stopped_i unused: remove

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 91e639a57e5c7336dd79eb55277502bdd58af141..215bcaab8830fc9b203e66db76b0e0c8d2677646 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -107,7 +107,6 @@ class NonProductionCore(Elaboratable):
         self.busy_o = Signal(name="corebusy_o", reset_less=True)
 
         # start/stop and terminated signalling
-        self.core_stopped_i = Signal(reset_less=True)
         self.core_terminate_o = Signal(reset=0)  # indicates stopped
 
         # create per-FU instruction decoders (subsetted)

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 9df03bb05b4d5693f707fd72f0e400506703a30d..eff313307db5dd8c4ef48d32d03efac916e606c3 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -562,7 +562,6 @@ class TestIssuerInternal(Elaboratable):
                         m.next = "INSN_WAIT"
                 with m.Else():
                     # tell core it's stopped, and acknowledge debug handshake
-                    comb += core.core_stopped_i.eq(1)
                     comb += dbg.core_stopped_i.eq(1)
                     # while stopped, allow updating the PC and SVSTATE
                     with m.If(self.pc_i.ok):
@@ -737,7 +736,6 @@ class TestIssuerInternal(Elaboratable):
                             m.next = "PRED_SKIP"
 
                 with m.Else():
-                    comb += core.core_stopped_i.eq(1)
                     comb += dbg.core_stopped_i.eq(1)
                     # while stopped, allow updating the PC and SVSTATE
                     with m.If(self.pc_i.ok):