tex->tex.macrotile[level]) {
r300->rws->buffer_set_tiling(tex->buf, r300->cs,
tex->tex.microtile, tex->tex.macrotile[level],
+ 0, 0, 0, 0, 0,
tex->tex.stride_in_bytes[0]);
tex->surface_level = level;
struct r600_screen *rscreen = (struct r600_screen*)screen;
rscreen->ws->buffer_set_tiling(resource->buf,
+ NULL,
surface->level[0].mode >= RADEON_SURF_MODE_1D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
surface->level[0].mode >= RADEON_SURF_MODE_2D ?
struct r600_screen *rscreen = (struct r600_screen*)screen;
rscreen->ws->buffer_set_tiling(resource->buf,
+ NULL,
surface->level[0].mode >= RADEON_SURF_MODE_1D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
surface->level[0].mode >= RADEON_SURF_MODE_2D ?
}
static void radeon_bo_set_tiling(struct pb_buffer *_buf,
+ struct radeon_winsys_cs *rcs,
enum radeon_bo_layout microtiled,
enum radeon_bo_layout macrotiled,
unsigned bankw, unsigned bankh,
uint32_t pitch)
{
struct radeon_bo *bo = get_radeon_bo(_buf);
+ struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
struct drm_radeon_gem_set_tiling args;
memset(&args, 0, sizeof(args));
+ /* Tiling determines how DRM treats the buffer data.
+ * We must flush CS when changing it if the buffer is referenced. */
+ if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
+ cs->flush_cs(cs->flush_data, 0);
+ }
+
while (p_atomic_read(&bo->num_active_ioctls)) {
sched_yield();
}
RADEON_TILING_EG_BANKW_SHIFT;
args.tiling_flags |= (bankh & RADEON_TILING_EG_BANKH_MASK) <<
RADEON_TILING_EG_BANKH_SHIFT;
- args.tiling_flags |= (eg_tile_split_rev(tile_split) &
- RADEON_TILING_EG_TILE_SPLIT_MASK) <<
- RADEON_TILING_EG_TILE_SPLIT_SHIFT;
+ if (tile_split) {
+ args.tiling_flags |= (eg_tile_split_rev(tile_split) &
+ RADEON_TILING_EG_TILE_SPLIT_MASK) <<
+ RADEON_TILING_EG_TILE_SPLIT_SHIFT;
+ }
args.tiling_flags |= (stencil_tile_split &
RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK) <<
RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
* \note microtile and macrotile are not bitmasks!
*/
void (*buffer_set_tiling)(struct pb_buffer *buf,
+ struct radeon_winsys_cs *rcs,
enum radeon_bo_layout microtile,
enum radeon_bo_layout macrotile,
unsigned bankw, unsigned bankh,