gallium/radeon: Fix r300g tiling breakage.
authorMichel Dänzer <michel.daenzer@amd.com>
Wed, 16 May 2012 21:52:19 +0000 (23:52 +0200)
committerMichel Dänzer <michel@daenzer.net>
Wed, 16 May 2012 21:52:19 +0000 (23:52 +0200)
Commit 11f056a3f0b87e86267efa8b5ac9d36a343c9dc1 broke the r300g build. Fix it
up, and reinstate some code which isn't needed by r600g and radeonsi but is
by r300g.

src/gallium/drivers/r300/r300_state.c
src/gallium/drivers/r300/r300_texture.c
src/gallium/drivers/r600/r600_texture.c
src/gallium/drivers/radeonsi/r600_texture.c
src/gallium/winsys/radeon/drm/radeon_drm_bo.c
src/gallium/winsys/radeon/drm/radeon_winsys.h

index 812fe39155a9a31fe0e05ce279d815133b3eb471..e025c2fcd1e2d7eb1c84b423ac49ab6098844297 100644 (file)
@@ -713,6 +713,7 @@ static void r300_tex_set_tiling_flags(struct r300_context *r300,
         tex->tex.macrotile[level]) {
         r300->rws->buffer_set_tiling(tex->buf, r300->cs,
                 tex->tex.microtile, tex->tex.macrotile[level],
+                0, 0, 0, 0, 0,
                 tex->tex.stride_in_bytes[0]);
 
         tex->surface_level = level;
index c9af04fac5d76a40a0a7d2818b67a8c9a706fa2f..6901722f6c1594f85260c3ce119aa0e0f6cedcbe 100644 (file)
@@ -917,6 +917,7 @@ r300_texture_create_object(struct r300_screen *rscreen,
 
     rws->buffer_set_tiling(tex->buf, NULL,
             tex->tex.microtile, tex->tex.macrotile[0],
+            0, 0, 0, 0, 0,
             tex->tex.stride_in_bytes[0]);
 
     return tex;
index 7a55d8e9d05b3416a70bf7b9770953da38624d09..d6f85c38c321431280449564298ffa511b1ea965 100644 (file)
@@ -451,6 +451,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
        struct r600_screen *rscreen = (struct r600_screen*)screen;
 
        rscreen->ws->buffer_set_tiling(resource->buf,
+                                      NULL,
                                       surface->level[0].mode >= RADEON_SURF_MODE_1D ?
                                       RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
                                       surface->level[0].mode >= RADEON_SURF_MODE_2D ?
index 80d5c7c0ee3cea3b20b67e7587d798cef410502b..8a62d68ff869d995a980a8b6a71d5d233e4cb854 100644 (file)
@@ -461,6 +461,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
        struct r600_screen *rscreen = (struct r600_screen*)screen;
 
        rscreen->ws->buffer_set_tiling(resource->buf,
+                                      NULL,
                                       surface->level[0].mode >= RADEON_SURF_MODE_1D ?
                                       RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
                                       surface->level[0].mode >= RADEON_SURF_MODE_2D ?
index 86d35c19de6c6ef8df6a7c31e97d81e001e8e6e6..2626586afd6ce340ac4f7e7a670dfdcfaca5c692 100644 (file)
@@ -684,6 +684,7 @@ static void radeon_bo_get_tiling(struct pb_buffer *_buf,
 }
 
 static void radeon_bo_set_tiling(struct pb_buffer *_buf,
+                                 struct radeon_winsys_cs *rcs,
                                  enum radeon_bo_layout microtiled,
                                  enum radeon_bo_layout macrotiled,
                                  unsigned bankw, unsigned bankh,
@@ -693,10 +694,17 @@ static void radeon_bo_set_tiling(struct pb_buffer *_buf,
                                  uint32_t pitch)
 {
     struct radeon_bo *bo = get_radeon_bo(_buf);
+    struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
     struct drm_radeon_gem_set_tiling args;
 
     memset(&args, 0, sizeof(args));
 
+    /* Tiling determines how DRM treats the buffer data.
+     * We must flush CS when changing it if the buffer is referenced. */
+    if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
+        cs->flush_cs(cs->flush_data, 0);
+    }
+
     while (p_atomic_read(&bo->num_active_ioctls)) {
         sched_yield();
     }
@@ -713,9 +721,11 @@ static void radeon_bo_set_tiling(struct pb_buffer *_buf,
         RADEON_TILING_EG_BANKW_SHIFT;
     args.tiling_flags |= (bankh & RADEON_TILING_EG_BANKH_MASK) <<
         RADEON_TILING_EG_BANKH_SHIFT;
-    args.tiling_flags |= (eg_tile_split_rev(tile_split) &
-                         RADEON_TILING_EG_TILE_SPLIT_MASK) <<
-        RADEON_TILING_EG_TILE_SPLIT_SHIFT;
+    if (tile_split) {
+       args.tiling_flags |= (eg_tile_split_rev(tile_split) &
+                             RADEON_TILING_EG_TILE_SPLIT_MASK) <<
+           RADEON_TILING_EG_TILE_SPLIT_SHIFT;
+    }
     args.tiling_flags |= (stencil_tile_split &
                          RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK) <<
         RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
index 443b20e25b9da2ccb50399f1da21a173ee336684..73160b63a2794172f8edfec012264551b9f798ab 100644 (file)
@@ -219,6 +219,7 @@ struct radeon_winsys {
      * \note microtile and macrotile are not bitmasks!
      */
     void (*buffer_set_tiling)(struct pb_buffer *buf,
+                              struct radeon_winsys_cs *rcs,
                               enum radeon_bo_layout microtile,
                               enum radeon_bo_layout macrotile,
                               unsigned bankw, unsigned bankh,