start integrating gpio / mux bus generation

diff --git a/src/bsv/bus_transactors.py b/src/bsv/bus_transactors.py
index d8857fe56b2294fc36eccb788a9eee7a897cfe46..b4ebefd5d4d37ed7b9b842382f16c5e9e8841792 100644 (file)
--- a/src/bsv/bus_transactors.py
+++ b/src/bsv/bus_transactors.py
@@ -1,42 +1,40 @@
 
 axi4_lite = '''
-package bus;
+// this file is auto-generated, please do not edit
+package gpio_instance;
+    /*==== Package imports ==== */
+    import TriState          ::*;
+    import Vector                ::*;
+    import BUtils::*;
+    import ConfigReg            ::*;
+    /*============================ */
+    /*===== Project Imports ===== */
+    import Semi_FIFOF        :: *;
+    import AXI4_Lite_Types   :: *;
+    import gpio   :: *;
+    import mux   :: *;
+    import pinmux   :: *;
+    /*============================ */
 
-  /*=== Project imports ===*/
-  import AXI4_Lite_Types::*;
-  import PinTop::*;
-  import pinmux::*;
-  import Semi_FIFOF::*;
-  /*======================*/
-
-  interface Ifc_bus;
-    interface AXI4_Lite_Slave_IFC #({0}, {1}, 0) axi_side;
+  // instantiation template
+    interface GPIO_real;
     interface PeripheralSide peripheral_side;
-  endinterface
-
-  module mkbus(Ifc_bus);
-    Ifc_PintTop pintop <-mkPinTop;
-    AXI4_Lite_Slave_Xactor_IFC#({0}, {1}, 0) slave_xactor <-
-                                                    mkAXI4_Lite_Slave_Xactor();
-    rule read_transaction;
-      let req<-pop_o(slave_xactor.o_rd_addr);
-      let {{err,data}}=pintop.read(req.araddr);
-      AXI4_Lite_Rd_Data#({0}, 0) r = AXI4_Lite_Rd_Data {{
-                                  rresp: err?AXI4_LITE_SLVERR:AXI4_LITE_OKAY,
-                                  rdata: zeroExtend(data) , ruser: 0}};
-      slave_xactor.i_rd_data.enq(r);
-    endrule
+    interface GPIO_config#(32) bankA_config;
+        interface AXI4_Lite_Slave_IFC#({0},{1},{2}) bankA_slave;
+    interface GPIO_config#(15) bankB_config;
+        interface AXI4_Lite_Slave_IFC#({0},{1},{2}) bankB_slave;
 
-    rule write_transaction;
-      let addr_req<-pop_o(slave_xactor.o_wr_addr);
-      let data_req<-pop_o(slave_xactor.o_wr_data);
-      let err<-pintop.write(addr_req.awaddr, data_req.wdata);
-      let b = AXI4_Lite_Wr_Resp {{bresp: err?AXI4_LITE_SLVERR:AXI4_LITE_OKAY,
-                                buser: ?}};
-      slave_xactor.i_wr_resp.enq (b);
-    endrule
-    interface axi_side= slave_xactor.axi_side;
-    interface peripheral_side=pintop.peripheral_side;
+    interface MUX_config#(32) muxbankA_config;
+        interface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxbankA_slave;
+    interface MUX_config#(15) muxbankB_config;
+        interface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxbankB_slave;
+    endinterface
+  (*synthesize*)
+  module mkgpio_real(GPIO_real);
+    Ifc_pinmux pinmux <-mkpinmux;
+    // gpio/mux declarations
+{3}
+    interface peripheral_side=pinmux.peripheral_side;
   endmodule
 endpackage
 '''

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 0bbfc19681c989a027792ed8f64eb89279823977..bfcc09eb2ad7a58a83d9b5769910fd529d0aa1a1 100644 (file)
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -304,5 +304,8 @@ endpackage
 def write_bvp(bvp, p, ifaces):
     # ######## Generate bus transactors ################
     with open(bvp, 'w') as bsv_file:
-        bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH))
+        gpiodecl = '// TODO'
+        bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH,
+                                        0, # USERSPACE
+                                        gpiodecl))
     # ##################################################