Fix sense of "invert" signal

We want to put "1" in the mask, if the operation is to be performed.
The actual CR bits are: LT, GT, EQ and SO.
So, for those, we just copy the bit directly to the mask, as they are.
For GE, LE, NE and NS, we want to invert the bit first.

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index a5f7304f08771a3ddaaca9a79eac6955e17ff2a3..6632185710c506f9e612bc68755629759d2180d6 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -124,28 +124,28 @@ def get_predcr(m, mask, name):
     with m.Switch(mask):
         with m.Case(SVP64PredCR.LT.value):
             comb += idx.eq(0)
-            comb += invert.eq(1)
+            comb += invert.eq(0)
         with m.Case(SVP64PredCR.GE.value):
             comb += idx.eq(0)
-            comb += invert.eq(0)
+            comb += invert.eq(1)
         with m.Case(SVP64PredCR.GT.value):
             comb += idx.eq(1)
-            comb += invert.eq(1)
+            comb += invert.eq(0)
         with m.Case(SVP64PredCR.LE.value):
             comb += idx.eq(1)
-            comb += invert.eq(0)
+            comb += invert.eq(1)
         with m.Case(SVP64PredCR.EQ.value):
             comb += idx.eq(2)
-            comb += invert.eq(1)
+            comb += invert.eq(0)
         with m.Case(SVP64PredCR.NE.value):
             comb += idx.eq(1)
-            comb += invert.eq(0)
+            comb += invert.eq(1)
         with m.Case(SVP64PredCR.SO.value):
             comb += idx.eq(3)
-            comb += invert.eq(1)
+            comb += invert.eq(0)
         with m.Case(SVP64PredCR.NS.value):
             comb += idx.eq(3)
-            comb += invert.eq(0)
+            comb += invert.eq(1)
     return idx, invert