use simpler logic for s_o_ready and d_valid

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 7196e1d66118b60545a7ed82af6117f17765e486..0c198aa7ce4ff41c491b353509aa1d413b57f4ba 100644 (file)
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -528,18 +528,11 @@ class ControlBase:
         if not self.p.stage_ctl:
             return m
 
-        # when the pipeline (buffered or otherwise) says "ready",
-        # test the *stage* "ready".
-
-        with m.If(self.p._o_ready):
-            m.d.comb += self.p.s_o_ready.eq(self.stage.p_o_ready)
-        with m.Else():
-            m.d.comb += self.p.s_o_ready.eq(0)
-
-        with m.If(self.n.i_ready):
-            m.d.comb += self.n.d_valid.eq(self.stage.d_valid)
-        with m.Else():
-            m.d.comb += self.n.d_valid.eq(0)
+        # intercept the previous (outgoing) "ready", combine with stage ready
+        m.d.comb += self.p.s_o_ready.eq(self.p._o_ready & self.stage.p_o_ready)
+
+        # intercept the next (incoming) "ready" and combine it with data valid
+        m.d.comb += self.n.d_valid.eq(self.n.i_ready & self.stage.d_valid)
 
         return m