allow rtlil file to be created in cordic

diff --git a/src/ieee754/cordic/test/test_fp_pipe.py b/src/ieee754/cordic/test/test_fp_pipe.py
index 698efc95a65ca0fba7895f772b0bcf4bd2df3d1a..56f853c7f9a8f3a80c5e6800a9f77de7fc61d0ff 100644 (file)
--- a/src/ieee754/cordic/test/test_fp_pipe.py
+++ b/src/ieee754/cordic/test/test_fp_pipe.py
@@ -17,10 +17,10 @@ class SinCosTestCase(FHDLTestCase):
         pspec = FPCordicPipeSpec(width=32, rounds_per_stage=4, num_rows=1)
         m.submodules.dut = dut = FPCordicBasePipe(pspec)
 
-
-        # vl = rtlil.convert(dut, ports=dut.ports())
-        # with open("test_cordic_pipe_sin_cos.il", "w") as f:
-        #     f.write(vl)
+        # write out module (useful for seeing what's going on)
+        vl = rtlil.convert(dut, ports=dut.ports())
+        with open("test_cordic_pipe_sin_cos.il", "w") as f:
+            f.write(vl)
 
         z = Signal(dut.p.data_i.a.shape())
         z_valid = Signal()