add traptype and trapaddr to PowerDecoder2. idea is to actually *change*

the instruction depending on conditions detected by the decoder

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 27cd5fa310b56eb4614af9b19a0b6d162bfd32a5..5aca9d851a3f466e59c8b04eb5a477e4dd102ad7 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -18,6 +18,13 @@ from soc.decoder.power_enums import (InternalOp, CryIn, Function,
 
 from soc.regfile.regfiles import FastRegs
 
+# see traptype (and trap main_stage.py)
+
+TT_FP = 1<<0
+TT_PRIV = 1<<1
+TT_TRAP = 1<<2
+TT_ADDR = 1<<3
+
 
 def instr_is_privileged(m, op, insn):
     """determines if the instruction is privileged or not
@@ -532,6 +539,8 @@ class Decode2ToExecute1Type(RecordObject):
         self.byte_reverse  = Signal(reset_less=True)
         self.sign_extend  = Signal(reset_less=True)# do we need this?
         self.update  = Signal(reset_less=True) # LD/ST is "update" variant
+        self.traptype  = Signal(4, reset_less=True) # see trap main_stage.py
+        self.trapaddr  = Signal(13, reset_less=True)
 
 
 class PowerDecode2(Elaboratable):
@@ -647,7 +656,19 @@ class PowerDecode2(Elaboratable):
         comb += e.input_cr.eq(op.cr_in)   # condition reg comes in
         comb += e.output_cr.eq(op.cr_out) # condition reg goes in
 
+        with m.If(op.internal_op == InternalOp.OP_TRAP):
+            comb += e.traptype.eq(TT_TRAP) # request trap interrupt
+            comb += e.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
+
+        return m
 
+        # privileged instruction
+        with m.If(instr_is_privileged(m, op.internal_op, e.insn) &
+                  msr[MSR_PR]):
+            # privileged instruction trap
+            comb += op.internal_op.eq(InternalOp.OP_TRAP)
+            comb += e.traptype.eq(TT_PRIV) # request privileged instruction
+            comb += e.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
         return m
 
     def regspecmap(self, regfile, regname):

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 17a9da84e2e467ef34ccff500ea17fed89bca619..fe018d8f1de5ae69b1814d19346b3450392fd5e1 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -33,11 +33,15 @@ MSR_LE  = (63 - 63)    # Little Endian
 
 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
 
-PI_PRIV = (63 - 43)    # 1 if FP exception
+# note that these correspond to trap_input_record.traptype bits 0,1,2,3
+# (TODO: add more?)
+
+PI_FP   = (63 - 43)    # 1 if FP exception
 PI_PRIV = (63 - 45)    # 1 if privileged interrupt
 PI_TRAP = (63 - 46)    # 1 if exception is "trap" type
 PI_ADR  = (63 - 47)    # 0 if SRR0 = address of instruction causing exception
 
+
 def msr_copy(msr_o, msr_i, zero_me=True):
     """
     -- ISA says this: