fix syntax errors and use correct FastRegs (SRR0/1 not SRR1/2)

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 28a68d18cc04d7ca81847dd56c66f36c61a9389e..1dc9b37f141fd95559be53bb973dc863a7b8308e 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -220,6 +220,7 @@ class DecodeOut(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
+        op = self.dec.op
 
         # select Register out field
         with m.Switch(self.sel_in):

diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index 31d79a87e51ab499a1c6d55b9feb3638d1d2301d..63435ae220d21ef7b3ccd89420908311cc535306 100644 (file)
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -85,8 +85,8 @@ def regspec_decode(e, regfile, name):
         CTR = 1<<FastRegs.CTR
         LR = 1<<FastRegs.LR
         TAR = 1<<FastRegs.TAR
+        SRR0 = 1<<FastRegs.SRR0
         SRR1 = 1<<FastRegs.SRR1
-        SRR2 = 1<<FastRegs.SRR2
         if name in ['cia', 'nia']:
             return Const(1), PC, PC # TODO: detect read-conditions
         if name == 'msr':

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index ba732bedd81c3dba21dbecb19fa03813ff15859b..a53ef5ab4be343d7225641b8060e6b06cc9c3d97 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -58,8 +58,8 @@ class FastRegs(RegFileArray):
     CTR = 2
     LR = 3
     TAR = 4
-    SRR1 = 5
-    SRR2 = 6
+    SRR0 = 5
+    SRR1 = 6
     def __init__(self):
         super().__init__(64, 8)
         self.w_ports = [self.write_port("dest1"),