Check the PC value at the end of each instruction

Useful for checking that the PC really points to the next instruction,
after fetching a prefixed instruction.

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 271d70642053b18bf29037a3a181e66103b52bd8..98d428400a222bfd30533f1fb979ed31c7c41ab2 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -172,6 +172,12 @@ def check_regs(dut, sim, core, test, code):
     dut.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code)))
     dut.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
 
+    # Check the PC as well
+    state = core.regs.rf['state']
+    pc = yield state.r_ports['cia'].data_o
+    e_pc = sim.pc.CIA.value
+    dut.assertEqual(e_pc, pc)
+
 
 def wait_for_busy_hi(cu):
     while True: