more SVP64 enums

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 0cee6124c3e4cb68fa57a66d27987ea7890fac9d..10357bd710ce0f0621d162a949cbf236784d0b0f 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -165,6 +165,19 @@ class SVP64RMMode(Enum):
     SATURATE = 3
     PREDRES = 4
 
+@unique
+class SVP64width(Enum):
+    DEFAULT = 0
+    EW_32 = 1
+    EW_16 = 2
+    EW_8 = 3
+
+@unique
+class SVP64subvl(Enum):
+    VEC1 = 0
+    VEC2 = 1
+    VEC3 = 2
+    VEC4 = 3
 
 # supported instructions: make sure to keep up-to-date with CSV files
 # just like everything else

diff --git a/src/soc/sv/svp64.py b/src/soc/sv/svp64.py
index d99332151a75e3cd14f2780d5ffafbe8f30d0116..da9d76273d90c43de3809d2d0d42f284a23be87c 100644 (file)
--- a/src/soc/sv/svp64.py
+++ b/src/soc/sv/svp64.py
@@ -16,8 +16,8 @@ https://libre-soc.org/openpower/sv/svp64/
 | MODE        | `19:23`    | changes Vector behaviour               |
 """
 
-from nmigen import Record
-
+from nmigen import Record, Elaboratable, Module, Signal
+from soc.decoder.power_enums import SVP64RMMode
 
 # in nMigen, Record begins at the LSB and fills upwards
 class SVP64Rec(Record):
@@ -54,3 +54,6 @@ Arithmetic:
 11     inv     CR-bit  Rc=1: pred-result CR sel
 11     inv     sz RC1  Rc=0: pred-result z/nonz
 """
+
+class SVP64RMMode(Elaboratable):
+    pass