include (but do not use) FreePDK45 in experiments10

diff --git a/experiments10_verilog/coriolis2/settings.py b/experiments10_verilog/coriolis2/settings.py
index a0a92b5023faf8975d929427c4882c1f7fc5282a..e4e3362cd24142fed2499339a92f84548000a38a 100644 (file)
--- a/experiments10_verilog/coriolis2/settings.py
+++ b/experiments10_verilog/coriolis2/settings.py
@@ -2,13 +2,41 @@
 
 from __future__ import print_function
 import os
-import Cfg
-import CRL
 import Viewer
 #import node180.scn6m_deep_09
-import symbolic.cmos45
 from   helpers       import overlay, l, u, n
 
+import os
+import socket
+import helpers
+
+NdaDirectory = None
+if os.environ.has_key('NDA_TOP'):
+    NdaDirectory = os.environ['NDA_TOP']
+if not NdaDirectory:
+    hostname = socket.gethostname()
+    if hostname.startswith('lepka'):
+        NdaDirectory = '/dsk/l1/jpc/crypted/soc/techno'
+        if not os.path.isdir(NdaDirectory):
+            print ('[ERROR] You forgot to mount the NDA encrypted directory, stupid!')
+    else:
+        NdaDirectory = '/users/soft/techno/techno'
+helpers.setNdaTopDir( NdaDirectory )
+
+import CRL
+import Cfg
+from   helpers import overlay, l, u, n
+
+# select one or other of these
+if False:
+    from   NDA.node45.freepdk45_c4m import techno, FlexLib, LibreSOCIO
+    techno.setup()
+    FlexLib.setup()
+    LibreSOCIO.setup()
+else:
+    import symbolic.cmos45
+
+
 if os.environ.has_key('CELLS_TOP'):
     cellsTop = os.environ['CELLS_TOP']
 else:
@@ -35,7 +63,7 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
     af  = CRL.AllianceFramework.get()
     env = af.getEnvironment()
-    env.setCLOCK( '^sys_clk|^ck|^jtag_tck' )
+    env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' )
     env.setPOWER( 'vdd' )
     env.setGROUND( 'vss' )
     env.addSYSTEM_LIBRARY( library=cellsTop+'/niolib',

diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py
index 4aa415ce51af0894897e39868b7824c643d33ffa..a652193e714b1deea46d77da282e8f59334c1844 100644 (file)
--- a/experiments10_verilog/doDesign.py
+++ b/experiments10_verilog/doDesign.py
@@ -14,6 +14,7 @@ from   plugins.alpha.block.block         import Block
 from   plugins.alpha.block.configuration import IoPin
 from   plugins.alpha.block.configuration import GaugeConf
 from   plugins.alpha.core2chip.niolib    import CoreToChip
+#from   plugins.alpha.core2chip.libresocio    import CoreToChip
 from   plugins.alpha.chip.configuration  import ChipConf
 from   plugins.alpha.chip.chip           import Chip
 
@@ -74,6 +75,7 @@ def scriptMain ( **kw ):
         adderConf.bColumns = 2
         adderConf.bRows = 2
         adderConf.chipConf.name = 'chip'
+        #adderConf.chipConf.ioPadGauge = 'LibreSOCIO'
         adderConf.chipConf.ioPadGauge = 'niolib'
         adderConf.coreSize = ( l(2000), l(2000) )
         adderConf.chipSize = ( l(5900), l(5900) )