whoops fpnorm out by one bit in new FPMSBHigh class

diff --git a/src/ieee754/fcvt/test/up_fcvt_data_16_32.py b/src/ieee754/fcvt/test/up_fcvt_data_16_32.py
index 24abc340d4bbee139f4ebe7d295e19fc97d2b041..2dbcb7fbf8a5d66d0630280249ebaab8d94531a9 100644 (file)
--- a/src/ieee754/fcvt/test/up_fcvt_data_16_32.py
+++ b/src/ieee754/fcvt/test/up_fcvt_data_16_32.py
@@ -1,3 +1,4 @@
 def regressions():
+    yield 0x110,
     yield 0x7e83,
     yield 0xaf47,

diff --git a/src/ieee754/fpcommon/postnormalise.py b/src/ieee754/fpcommon/postnormalise.py
index 5bfb447c958129c450e3968bb78d2f3d527442c6..196d158a00f63ccf2c919051da1cfca4e2442203 100644 (file)
--- a/src/ieee754/fpcommon/postnormalise.py
+++ b/src/ieee754/fpcommon/postnormalise.py
@@ -80,7 +80,7 @@ class FPNorm1ModSingle(Elaboratable):
         msr = MultiShiftRMerge(mwid+2, espec)
         m.submodules.multishift_r = msr
 
-        msb = FPMSBHigh(mwid, espec[0], True)
+        msb = FPMSBHigh(mwid+1, espec[0], True)
         m.submodules.norm_msb = msb
 
         m.d.comb += i.eq(self.i)
@@ -97,7 +97,6 @@ class FPNorm1ModSingle(Elaboratable):
             with m.If(decrease):
                 # make sure that the amount to decrease by does NOT
                 # go below the minimum non-INF/NaN exponent
-                temp_m = Signal(mwid+1, reset_less=True)
                 m.d.comb += msb.limclz.eq(insel_z.exp_sub_n126)
                 m.d.comb += [
                     # cat round and guard bits back into the mantissa