'orangecrab': OrangeCrabR0_2_85k_Platform,
'arty_a7': ArtyA7_100Platform,
'isim': IcarusVersaPlatform,
+ 'rcs_arctic_tern_bmc_card':None, #TODO
'sim': None,
}[fpga]
toolchain = {'arty_a7': "yosys_nextpnr",
'orangecrab': 'Trellis',
'isim': 'Trellis',
'ulx3s': 'Trellis',
+ 'rcs_arctic_tern_bmc_card': 'Trellis',
'sim': None,
}.get(fpga, None)
dram_cls = {'arty_a7': None,
'orangecrab': MT41K64M16,
#'versa_ecp5': MT41K256M16,
'ulx3s': None,
+ 'rcs_arctic_tern_bmc_card': None, # TODO
'sim': MT41K256M16,
'isim': MT41K64M16,
}.get(fpga, None)