drop clock frequency to 25 mhz and disable abc9 (it fails to build)

diff --git a/src/ls2.py b/src/ls2.py
index cd3b4c8bd7c6066845d4c877d954ce3f68905299..78e4399413d09537c37fd16d8c5be4c7327d0611 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -271,11 +271,12 @@ if __name__ == "__main__":
                   fw_addr=fw_addr,
                   ddr_pins=ddr_pins,
                   uart_pins=uart_pins,
-                  firmware=firmware)
+                  firmware=firmware,
+                  clk_freq=25e6)
 
-    if toolchain == 'Trellis':
+    #if toolchain == 'Trellis':
         # add -abc9 option to yosys synth_ecp5
-        os.environ['NMIGEN_synth_opts'] = '-abc9'
+    #    os.environ['NMIGEN_synth_opts'] = '-abc9'
 
     if platform is not None:
         # build and upload it