if typ == 'out' or typ == 'inout':
ret.append(" rule con_%s%d_%s_out;" % (name, count, pname))
fname = self.pinname_out(pname)
- if not n.startswith('gpio'): # XXX EURGH! horrible hack
- n_ = "{0}{1}".format(n, count)
+ if not n.startswith('gpio'): # XXX EURGH! horrible hack
+ n_ = "{0}{1}".format(n, count)
else:
- n_ = n
+ n_ = n
if fname:
if p.get('outen'):
ps_ = ps + '_out'
(name, count, pname))
n_ = "{0}{1}".format(n, count)
n_ = '{0}.{1}'.format(n_, fname)
- n_ = self.ifname_tweak(pname, 'in', n_)
+ n_ = self.ifname_tweak(pname, 'in', n_)
ret.append(" {1}({0});".format(ps_, n_))
ret.append(" endrule")
return '\n'.join(ret)
size = len(self.peripheral.pinspecs)
return " Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
-
def axi_slave_name(self, name, ifacenum):
return ''
ret = [PBase.mk_pincon(self, name, count)]
size = len(self.peripheral.pinspecs)
ret.append(eint_pincon_template.format(size))
- ret.append(" rule con_%s%d_io_in;" % (name, count))
+ ret.append(" rule con_%s%d_io_in;" % (name, count))
ret.append(" wr_interrupt <= ({")
- for idx, p in enumerate(self.peripheral.pinspecs):
+ for idx, p in enumerate(self.peripheral.pinspecs):
pname = p['name']
sname = self.peripheral.pname(pname).format(count)
ps = "pinmux.peripheral_side.%s" % sname
- comma = '' if idx == size-1 else ','
- ret.append(" {0}{1}".format(ps, comma))
+ comma = '' if idx == size - 1 else ','
+ ret.append(" {0}{1}".format(ps, comma))
ret.append(" });")
ret.append(" endrule")
name = name.upper()
mname = 'mux' + name[4:]
mname = mname.upper()
- print "AXIslavenum", name, mname
+ print "AXIslavenum", name, mname
(ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
- (ret2, x) = PBase.axi_slave_idx(self, idx+1, mname, ifacenum)
+ (ret2, x) = PBase.axi_slave_idx(self, idx + 1, mname, ifacenum)
return ("%s\n%s" % (ret, ret2), 2)
def mkslow_peripheral(self, size=0):
- print "gpioslow", self.peripheral, dir(self.peripheral)
+ print "gpioslow", self.peripheral, dir(self.peripheral)
size = len(self.peripheral.pinspecs)
return " MUX#(%d) mux{0} <- mkmux();\n" % size + \
" GPIO#(%d) gpio{0} <- mkgpio();" % size
if slow:
self.slow = slow(ifacename)
self.slow.peripheral = self
- for fname in ['slowimport', 'slowifdecl', 'slowifdeclmux',
+ for fname in ['slowimport', 'slowifdecl', 'slowifdeclmux',
'mkslow_peripheral',
'mk_connection', 'mk_cellconn', 'mk_pincon']:
fn = CallFn(self, fname)
os.path.join(bp, 'Makefile'))
cwd = os.path.join(cwd, 'bsv_lib')
for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
- 'gpio.bsv', 'mux.bsv',
- 'AXI4_Types.bsv', 'defined_types.bsv',
- 'AXI4_Fabric.bsv', 'Uart16550.bsv',
- 'AXI4_Lite_Fabric.bsv', 'ConcatReg.bsv',
- 'Uart_bs.bsv', 'RS232_modified.bsv',
+ 'gpio.bsv', 'mux.bsv',
+ 'AXI4_Types.bsv', 'defined_types.bsv',
+ 'AXI4_Fabric.bsv', 'Uart16550.bsv',
+ 'AXI4_Lite_Fabric.bsv', 'ConcatReg.bsv',
+ 'Uart_bs.bsv', 'RS232_modified.bsv',
'AXI4Lite_AXI4_Bridge.bsv',
- 'I2C_top.bsv', 'I2C_Defs.bsv',
- 'plic.bsv', 'Cur_Cycle.bsv',
- 'ClockDiv.bsv', 'axi_addr_generator.bsv',
- 'jtagdtm_new.bsv', 'jtagdefines.bsv',
+ 'I2C_top.bsv', 'I2C_Defs.bsv',
+ 'plic.bsv', 'Cur_Cycle.bsv',
+ 'ClockDiv.bsv', 'axi_addr_generator.bsv',
+ 'jtagdtm_new.bsv', 'jtagdefines.bsv',
'sdcard_dummy.bsv',
- 'pwm.bsv', 'qspi.bsv', 'qspi.defs',
+ 'pwm.bsv', 'qspi.bsv', 'qspi.defs',
]:
shutil.copyfile(os.path.join(cwd, fname),
os.path.join(bl, fname))
`define USERSPACE 0
// TODO: work out if these are needed
-`define PWM_AXI4Lite
+`define PWM_AXI4Lite
`define PRFDEPTH 6
`define VADDR 39
`define DCACHE_BLOCK_SIZE 4