radeonsi: implement R9G9B9E5 render target and image store support on gfx10.3

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>

diff --git a/src/amd/registers/gfx10.json b/src/amd/registers/gfx10.json
index 5c2b251ca4368f94f72b3cc69ba995659fbd2521..77a34a75072b4e1d0d6ef5e54766ade9794317dc 100644 (file)
--- a/src/amd/registers/gfx10.json
+++ b/src/amd/registers/gfx10.json
@@ -89,6 +89,32 @@
     {"name": "CB_RESERVED", "value": 7}
    ]
   },
+  "CB_COLOR0_INFO__FORMAT": {
+   "entries": [
+    {"name": "COLOR_INVALID", "value": 0},
+    {"name": "COLOR_8", "value": 1},
+    {"name": "COLOR_16", "value": 2},
+    {"name": "COLOR_8_8", "value": 3},
+    {"name": "COLOR_32", "value": 4},
+    {"name": "COLOR_16_16", "value": 5},
+    {"name": "COLOR_10_11_11", "value": 6},
+    {"name": "COLOR_11_11_10", "value": 7},
+    {"name": "COLOR_10_10_10_2", "value": 8},
+    {"name": "COLOR_2_10_10_10", "value": 9},
+    {"name": "COLOR_8_8_8_8", "value": 10},
+    {"name": "COLOR_32_32", "value": 11},
+    {"name": "COLOR_16_16_16_16", "value": 12},
+    {"name": "COLOR_32_32_32_32", "value": 14},
+    {"name": "COLOR_5_6_5", "value": 16},
+    {"name": "COLOR_1_5_5_5", "value": 17},
+    {"name": "COLOR_5_5_5_1", "value": 18},
+    {"name": "COLOR_4_4_4_4", "value": 19},
+    {"name": "COLOR_8_24", "value": 20},
+    {"name": "COLOR_24_8", "value": 21},
+    {"name": "COLOR_X24_8_32_FLOAT", "value": 22},
+    {"name": "COLOR_5_9_9_9", "value": 24}
+   ]
+  },
   "CBPerfClearFilterSel": {
    "entries": [
     {"name": "CB_PERF_CLEAR_FILTER_SEL_NONCLEAR", "value": 0},
@@ -5313,7 +5339,8 @@
     {"name": "SX_RT_EXPORT_1_5_5_5", "value": 7},
     {"name": "SX_RT_EXPORT_4_4_4_4", "value": 8},
     {"name": "SX_RT_EXPORT_16_16_GR", "value": 9},
-    {"name": "SX_RT_EXPORT_16_16_AR", "value": 10}
+    {"name": "SX_RT_EXPORT_16_16_AR", "value": 10},
+    {"name": "SX_RT_EXPORT_9_9_9_E5", "value": 11}
    ]
   },
   "SX_OPT_COMB_FCN": {
@@ -17262,7 +17289,7 @@
   "CB_COLOR0_INFO": {
    "fields": [
     {"bits": [0, 1], "name": "ENDIAN"},
-    {"bits": [2, 6], "name": "FORMAT"},
+    {"bits": [2, 6], "enum_ref": "CB_COLOR0_INFO__FORMAT", "name": "FORMAT"},
     {"bits": [7, 7], "name": "LINEAR_GENERAL"},
     {"bits": [8, 10], "name": "NUMBER_TYPE"},
     {"bits": [11, 12], "name": "COMP_SWAP"},

diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c
index ce19c428f1cfa8dfc1eea51eabbba9cdaac9ab2c..a9ec6fefc7f4932280e78d399262bda335487d55 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_compute_blit.c
+++ b/src/gallium/drivers/radeonsi/si_compute_blit.c
@@ -495,7 +495,8 @@ void si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, u
    image[1].u.tex.last_layer = dst->target == PIPE_TEXTURE_3D ? u_minify(dst->depth0, dst_level) - 1
                                                               : (unsigned)(dst->array_size - 1);
 
-   if (src->format == PIPE_FORMAT_R9G9B9E5_FLOAT)
+   if (sctx->chip_class < GFX10_3 &&
+       src->format == PIPE_FORMAT_R9G9B9E5_FLOAT)
       image[0].format = image[1].format = PIPE_FORMAT_R32_UINT;
 
    /* SNORM8 blitting has precision issues on some chips. Use the SINT

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 3156a60fabf85374aceefd190a7a44636cc5b834..2f156a0885f493210314fa3264a56c2834381615 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -237,6 +237,11 @@ static void si_emit_cb_render_state(struct si_context *sctx)
                sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
             }
             break;
+
+         case V_028C70_COLOR_5_9_9_9:
+            if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
+               sx_ps_downconvert |= V_028754_SX_RT_EXPORT_9_9_9_E5 << (i * 4);
+            break;
          }
       }
 
@@ -1414,7 +1419,8 @@ static void si_emit_db_render_state(struct si_context *sctx)
 /*
  * format translation
  */
-static uint32_t si_translate_colorformat(enum pipe_format format)
+static uint32_t si_translate_colorformat(enum chip_class chip_class,
+                                         enum pipe_format format)
 {
    const struct util_format_description *desc = util_format_description(format);
    if (!desc)
@@ -1427,6 +1433,10 @@ static uint32_t si_translate_colorformat(enum pipe_format format)
    if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
       return V_028C70_COLOR_10_11_11;
 
+   if (chip_class >= GFX10_3 &&
+       format == PIPE_FORMAT_R9G9B9E5_FLOAT) /* isn't plain */
+      return V_028C70_COLOR_5_9_9_9;
+
    if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
       return V_028C70_COLOR_INVALID;
 
@@ -2092,9 +2102,10 @@ static unsigned si_is_vertex_format_supported(struct pipe_screen *screen, enum p
    return usage;
 }
 
-static bool si_is_colorbuffer_format_supported(enum pipe_format format)
+static bool si_is_colorbuffer_format_supported(enum chip_class chip_class,
+                                               enum pipe_format format)
 {
-   return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
+   return si_translate_colorformat(chip_class, format) != V_028C70_COLOR_INVALID &&
           si_translate_colorswap(format, false) != ~0U;
 }
 
@@ -2160,7 +2171,7 @@ static bool si_is_format_supported(struct pipe_screen *screen, enum pipe_format
 
    if ((usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
                  PIPE_BIND_SHARED | PIPE_BIND_BLENDABLE)) &&
-       si_is_colorbuffer_format_supported(format)) {
+       si_is_colorbuffer_format_supported(sscreen->info.chip_class, format)) {
       retval |= usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
                          PIPE_BIND_SHARED);
       if (!util_format_is_pure_integer(format) && !util_format_is_depth_or_stencil(format))
@@ -2207,6 +2218,7 @@ static void si_choose_spi_color_formats(struct si_surface *surf, unsigned format
    case V_028C70_COLOR_4_4_4_4:
    case V_028C70_COLOR_10_11_11:
    case V_028C70_COLOR_11_11_10:
+   case V_028C70_COLOR_5_9_9_9:
    case V_028C70_COLOR_8:
    case V_028C70_COLOR_8_8:
    case V_028C70_COLOR_8_8_8_8:
@@ -2339,7 +2351,7 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa
       }
    }
 
-   format = si_translate_colorformat(surf->base.format);
+   format = si_translate_colorformat(sctx->chip_class, surf->base.format);
    if (format == V_028C70_COLOR_INVALID) {
       PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
    }

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 63a3571b0a54ef2e9d55c83233754b3a4ed653f2..242a23df1007a27a40f457e909c57f87b055fa25 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -257,7 +257,9 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
    }
 
    if (sscreen->info.chip_class >= GFX8 &&
-       (ptex->flags & SI_RESOURCE_FLAG_DISABLE_DCC || ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT ||
+       (ptex->flags & SI_RESOURCE_FLAG_DISABLE_DCC ||
+        (sscreen->info.chip_class < GFX10_3 &&
+         ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT) ||
         (ptex->nr_samples >= 2 && !sscreen->dcc_msaa_allowed)))
       flags |= RADEON_SURF_DISABLE_DCC;