Enable VL==0 vector instruction skip test case

diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
index 92e8522aecd8b5d3df0df7b630b24ef81a0e7817..3c90e71dd338b4aa7e0dccc092fd7ddda1ac1077 100644 (file)
--- a/src/soc/fu/alu/test/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -100,8 +100,7 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs,
                       initial_svstate=svstate)
 
-    @skip_case("VL hardware loop is not yet implemented")
-    def case_4_sv_check_vl_0(self):
+    def case_5_sv_check_vl_0(self):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
         isa = SVP64Asm([