code-shuffle on testing to prepare loading large files into memory

diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py
index 02c83281612c992227a4b792db9524e6b2265cb4..780fcba73474b195bc22a59c8f9e2ab3f4543d8c 100644 (file)
--- a/src/soc/bus/test/test_minerva.py
+++ b/src/soc/bus/test/test_minerva.py
@@ -38,7 +38,13 @@ class TestSRAMBareFetchUnit(BareFetchUnit):
     def __init__(self, pspec):
         super().__init__(pspec)
         # small 16-entry Memory
-        self.mem = Memory(width=self.data_wid, depth=32)
+        if (hasattr(pspec, "imem_test_depth") and
+            isinstance(pspec.imem_test_depth, int)):
+            depth = pspec.imem_test_depth
+        else:
+            depth = 32
+        print ("TestSRAMBareFetchUnit depth", depth)
+        self.mem = Memory(width=self.data_wid, depth=depth)
 
     def _get_memory(self):
         return self.mem

diff --git a/src/soc/config/test/test_fetch.py b/src/soc/config/test/test_fetch.py
index 00154dfde5ed2b49e9a32b56db5b02edcc9e05eb..f6f0901a2efc95df35beb3a20affb47f89874655 100644 (file)
--- a/src/soc/config/test/test_fetch.py
+++ b/src/soc/config/test/test_fetch.py
@@ -7,8 +7,10 @@ from soc.config.ifetch import ConfigFetchUnit
 from collections import namedtuple
 from nmigen.cli import rtlil
 
-from soc.config.test.test_loadstore import TestMemPspec 
+from soc.config.test.test_loadstore import TestMemPspec
 
+import sys
+sys.setrecursionlimit(10**6)
 
 def read_from_addr(dut, addr):
     yield dut.a_pc_i.eq(addr)
@@ -29,12 +31,13 @@ def read_from_addr(dut, addr):
     return res
 
 
-def tst_lsmemtype(ifacetype):
+def tst_lsmemtype(ifacetype, sram_depth=32):
     m = Module()
-    pspec = TestMemPspec(ldst_ifacetype=ifacetype, 
+    pspec = TestMemPspec(ldst_ifacetype=ifacetype,
                          imem_ifacetype=ifacetype, addr_wid=64,
                                                    mask_wid=4,
-                                                   reg_wid=32)
+                                                   reg_wid=32,
+                         imem_test_depth=sram_depth)
     dut = ConfigFetchUnit(pspec).fu
     vl = rtlil.convert(dut, ports=[]) # TODOdut.ports())
     with open("test_fetch_%s.il" % ifacetype, "w") as f:
@@ -64,5 +67,5 @@ def tst_lsmemtype(ifacetype):
         sim.run()
 
 if __name__ == '__main__':
-    tst_lsmemtype('test_bare_wb')
+    tst_lsmemtype('test_bare_wb', sram_depth=32768)
     tst_lsmemtype('testmem')

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 902d9747a96871e89923e053645775dd694a291e..39a1fd90e26cfbc1bb7679f97297ae8285ab99ce 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -10,7 +10,8 @@ from soc.regfile.regfiles import FastRegs
 
 class TestCase:
     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
-                       msr=0):
+                       msr=0,
+                       do_sim=True):
 
         self.program = program
         self.name = name
@@ -26,6 +27,8 @@ class TestCase:
         self.cr = cr
         self.mem = mem
         self.msr = msr
+        self.do_sim = do_sim
+
 
 class ALUHelpers:
 

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index d0d1c5e2350263207e41e7b22bcfd2c79e798fbb..45e6b283325bb6bc3567889930ad606d78ecad78 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -75,6 +75,10 @@ class TestIssuer(Elaboratable):
         comb += self.pc_o.eq(cur_pc)
         ilatch = Signal(32)
 
+        # allow debug access to current instruction and pc
+        self._current_insn = current_insn
+        self._cur_pc = cur_pc
+
         # next instruction (+4 on current)
         nia = Signal(64, reset_less=True)
         comb += nia.eq(cur_pc + 4)

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index e679fcd2a2197df36e42d840eb1d783078ecfec9..f4e4363aad94f8d44f9a336d7a054f8227a85fb3 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -37,22 +37,29 @@ from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
 
 def setup_i_memory(imem, startaddr, instructions):
     mem = imem
-    print ("insn before, init mem", mem.depth, mem.width, mem)
+    print ("insn before, init mem", mem.depth, mem.width, mem,
+                                    len(instructions))
     for i in range(mem.depth):
         yield mem._array[i].eq(0)
     yield Settle()
     startaddr //= 4 # instructions are 32-bit
     mask = ((1<<64)-1)
-    for insn, code in instructions:
+    for ins in instructions:
+        if isinstance(ins, tuple):
+            insn, code = ins
+        else:
+            insn, code = ins, ''
         msbs = (startaddr>>1) & mask
         val = yield mem._array[msbs]
-        print ("before set", hex(startaddr), hex(msbs), hex(val))
+        if insn != 0:
+            print ("before set", hex(startaddr), hex(msbs), hex(val), hex(insn))
         lsb = 1 if (startaddr & 1) else 0
         val = (val | (insn << (lsb*32))) & mask
         yield mem._array[msbs].eq(val)
         yield Settle()
-        print ("after  set", hex(startaddr), hex(msbs), hex(val))
-        print ("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
+        if insn != 0:
+            print ("after  set", hex(startaddr), hex(msbs), hex(val))
+            print ("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
         startaddr += 1
         startaddr = startaddr & mask
 
@@ -170,14 +177,14 @@ if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
     suite.addTest(TestRunner(AttnTestCase.test_data))
-    #suite.addTest(TestRunner(GeneralTestCases.test_data))
-    #suite.addTest(TestRunner(LDSTTestCase.test_data))
-    #suite.addTest(TestRunner(CRTestCase.test_data))
-    #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
-    #suite.addTest(TestRunner(LogicalTestCase.test_data))
-    #suite.addTest(TestRunner(ALUTestCase.test_data))
-    #suite.addTest(TestRunner(BranchTestCase.test_data))
-    #suite.addTest(TestRunner(SPRTestCase.test_data))
+    suite.addTest(TestRunner(GeneralTestCases.test_data))
+    suite.addTest(TestRunner(LDSTTestCase.test_data))
+    suite.addTest(TestRunner(CRTestCase.test_data))
+    suite.addTest(TestRunner(ShiftRotTestCase.test_data))
+    suite.addTest(TestRunner(LogicalTestCase.test_data))
+    suite.addTest(TestRunner(ALUTestCase.test_data))
+    suite.addTest(TestRunner(BranchTestCase.test_data))
+    suite.addTest(TestRunner(SPRTestCase.test_data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)

diff --git a/src/soc/simulator/program.py b/src/soc/simulator/program.py
index fdcea64201580ab7432f767f6a16c1c6d9580e7a..4cf9b9ffd52778e2a971178121f8979679b690b6 100644 (file)
--- a/src/soc/simulator/program.py
+++ b/src/soc/simulator/program.py
@@ -20,10 +20,15 @@ obj_fmt = "-be"
 
 class Program:
     def __init__(self, instructions):
-        if isinstance(instructions, list):
-            instructions = '\n'.join(instructions)
-        self.assembly = instructions + '\n' # plus final newline
-        self._assemble()
+        if isinstance(instructions, str): # filename
+            self.binfile = open(instructions, "rb")
+            self.assembly = '' # noo disassemble number fiiive
+            print ("program", self.binfile)
+        else:
+            if isinstance(instructions, list):
+                instructions = '\n'.join(instructions)
+            self.assembly = instructions + '\n' # plus final newline
+            self._assemble()
         self._instructions = list(self._get_instructions())
 
     def __enter__(self):