got icarus verilog model of QSPI working and it returns the same FFFFFFF

diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index 6872e3d4b051761a4509d3a4d3b714fe0eb2d440..5586e90f9abc452a55d85c23bf4925c3c6832932 100644 (file)
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -68,6 +68,7 @@ int main(void) {
 
        puts("fw..");
 #if 1
+#if 0
     // print out configuration parameters for QSPI
        volatile uint32_t *qspi_cfg = (uint32_t*)0xc0003000;
     for (int k=0; k < 10; k++) {
@@ -78,7 +79,7 @@ int main(void) {
         uart_writeuint32(tmp);
         puts("\n");
     }
-
+#endif
        volatile uint32_t *qspi = (uint32_t*)0x10000000;
     // let's not, eh? writel(0xDEAF0123, (unsigned long)&(qspi[0]));
     // tmp = readl((unsigned long)&(qspi[0]));

diff --git a/qspi_model/README.txt b/qspi_model/README.txt
index 4ec1d36e02fd667357bc1155e6992fe95f326986..725389facbdf86adcdb7acf5b8f486892428b4a8 100644 (file)
--- a/qspi_model/README.txt
+++ b/qspi_model/README.txt
@@ -1,12 +1,7 @@
-* download micron n25q model:
-https://media-www.micron.com/-/media/client/global/documents/products/sim-model/nor-flash/serial/bfm/n25q/n25q_256mb_18v_micronxip_vg15,-d-,tar.gz?rev=20813bd927aa4890863866045fd77241
-* at line 2039 and 2065 change "fork : CP_sendToBus"   and "join"
-  to                            "begin : CP_sendToBus" and "end"
-  (see n25q.patch)
-
-the micron n25q model contains the following copyright notice:
-Copyright 2013 Micron Technology, Inc. All rights reserved.
-(no license given, disclaimer noted)
-
-* download cyperss model:
+* download cypress model:
 https://community.infineon.com/gfawx74859/attachments/gfawx74859/NonVolatileRAM/994/1/Cy15b104qs.zip
+* unzip
+
+Copyright notices in cy15b104qs.v:
+Copyright (C) 2014 Spansion, LLC.
+(no explicit license given)

diff --git a/runsimsoc_hyperram.sh b/runsimsoc_hyperram.sh
index fcb6ecbb33df828d4e50411fb4168775f945c0f0..59723771c86631648f81da9eb21a470635795096 100755 (executable)
--- a/runsimsoc_hyperram.sh
+++ b/runsimsoc_hyperram.sh
@@ -5,13 +5,13 @@ LIB_DIR=./src/ecp5u
 
 HYPERRAM_DIR=./hyperram_model/s27kl0641/model
 
-QSPI_DIR=./qspi_model/N25Q256A11E_VG15/
+QSPI_DIR=./qspi_model/Cy15b104qs/model/
 
 # create the build_simsoc/top.il file with firmware baked-in
-#python3 src/ls2.py isim ./coldboot/coldboot.bin
+python3 src/ls2.py isim ./coldboot/coldboot.bin
 
 # do some voodoo magic to get icarus to be happy with the ilang file
-#yosys simsoc.ys
+yosys simsoc.ys
 
 # fix a bug in Lattice ECP5 models
 cp ${LIB_DIR}/DDRDLLA.v DDRDLLA.v
@@ -34,6 +34,6 @@ iverilog -Wall -g2012 -s simsoc_hyperram_tb -o simsoc \
     ${LIB_DIR}/ODDRX2DQSB.v ${LIB_DIR}/IDDRX2DQA.v \
     DDRDLLA.v \
         -I ${QSPI_DIR} -DN25Q128A13E \
-    ${QSPI_DIR}/code/N25Qxxx.v \
+    ${QSPI_DIR}/cy15b104qs.v \
        ${LIB_DIR}/CLKDIVF.v
 vvp -n simsoc -fst-speed

diff --git a/src/ls2.py b/src/ls2.py
index 5895641b618dd410c39f2212e2332f7da6c1740e..5a8546465e3e2f9af9c926cc53dd278006b27e03 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -683,7 +683,8 @@ def build_platform(fpga, firmware):
             Resource("spi_0", 0,
                      Subsignal("dq",   Pins("W2 V2 Y2 W1", dir="io")),
                      Subsignal("cs_n", Pins("R2", dir="o")),
-                     Attrs(PULLMODE="NONE", DRIVE="4", IO_TYPE="LVCMOS33"))
+                     Attrs(PULLMODE="NONE", DRIVE="8", SLEWRATE="FAST",
+                           IO_TYPE="LVCMOS33"))
         ]
         platform.add_resources(spi_0_ios)
         spi_0_pins = platform.request("spi_0", 0, dir={"dq":"io", "cs_n":"o"},

diff --git a/src/simsoc_hyperram_tb.v b/src/simsoc_hyperram_tb.v
index 1940560eb36ca4c73575554654e3a4b31be56032..7c59d6f5d59075de71616d4a54d2efdecd58c4a8 100644 (file)
--- a/src/simsoc_hyperram_tb.v
+++ b/src/simsoc_hyperram_tb.v
@@ -3,8 +3,6 @@
 
 `timescale 1 ns / 1 ns
 
-`include "include/DevParam.h"
-
 module simsoc_hyperram_tb;
   // GSR & PUR init requires for Lattice models
   GSR GSR_INST (
@@ -39,7 +37,6 @@ module simsoc_hyperram_tb;
     wire io_rwds;
 
     // SPI
-    wire spi_clk;
     wire spi_cs_n;
     wire spi_rst_n;
     wire [3:0] io_spi_dq;
@@ -62,17 +59,6 @@ s27kl0641
     .RESETNeg(o_resetn)
     );
 
-   N25Qxxx N25Qxxx
-     (
-      .S(spi_cs_n),
-      .C_(spi_clk),
-      .HOLD_DQ3(io_spi_dq[3]),
-      .DQ0(io_spi_dq[0]),
-      .DQ1(io_spi_dq[1]),
-      .Vcc(VCC_3V),
-      .Vpp_W_DQ2(io_spi_dq[2])
-      );
-
   // uart, LEDs, switches
   wire uart_tx ;
   reg uart_rx = 0;
@@ -101,8 +87,10 @@ s27kl0641
     .hyperram_0__ck__io(o_clk), 
     .hyperram_0__dq__io(io_dq),
     // Quad SPI
-    .spi_flash_4x_0__dq__io(io_spi_dq),
-    .spi_flash_4x_0__cs__io(spi_cs_n),
+    //.spi_flash_4x_0__dq__io(io_spi_dq),
+    //.spi_flash_4x_0__cs__io(spi_cs_n),
+    .spi_0_0__dq__io(io_spi_dq),
+    .spi_0_0__cs_n__io(spi_cs_n),
 
     // uart
     .uart_0__rx__io(uart_rx),
@@ -130,6 +118,16 @@ s27kl0641
     .rst_0__io(1'b0)
   );
 
+    cy15b104qs cy15b104qs
+     (
+      .CSNeg(spi_cs_n),
+      .SCK(simsoctop.spi0.spi_clk),
+      .RESETNeg(io_spi_dq[3]),
+      .SO(io_spi_dq[0]),
+      .SI(io_spi_dq[1]),
+      .WPNeg(io_spi_dq[2])
+      );
+
   initial
     begin
       $dumpfile("simsoc_hyperram.fst");
@@ -147,8 +145,6 @@ s27kl0641
   initial
     begin
       
-      spi_clk = top.spi0.spi_clk;
-
       // run for a set time period then exit
       #120000000;