move MMU Testcase to openpower.test

diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_rom.py b/src/soc/fu/mmu/test/test_issuer_mmu_rom.py
deleted file mode 100644 (file)
index a3e9ff1..0000000
--- a/src/soc/fu/mmu/test/test_issuer_mmu_rom.py
+++ /dev/null
@@ -1,69 +0,0 @@
-from nmigen import Module, Signal
-from soc.simple.test.test_runner import TestRunner
-from openpower.simulator.program import Program
-from openpower.endian import bigendian
-import unittest
-
-from openpower.test.common import (TestAccumulatorBase, skip_case, TestCase,
-                                ALUHelpers)
-
-def b(x):
-    return int.from_bytes(x.to_bytes(8, byteorder='little'),
-                          byteorder='big', signed=False)
-
-
-default_mem = { 0x10000:    # PARTITION_TABLE_2
-                       # PATB_GR=1 PRTB=0x1000 PRTS=0xb
-                b(0x800000000100000b),
-
-                0x30000:     # RADIX_ROOT_PTE
-                        # V = 1 L = 0 NLB = 0x400 NLS = 9
-                b(0x8000000000040009),
-
-                0x40000:     # RADIX_SECOND_LEVEL
-                        #         V = 1 L = 1 SW = 0 RPN = 0
-                           # R = 1 C = 1 ATT = 0 EAA 0x7
-                b(0xc000000000000187),
-
-                0x1000000:   # PROCESS_TABLE_3
-                       # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
-                b(0x40000000000300ad),
-            }
-
-
-class MMUTestCase(TestAccumulatorBase):
-    # MMU on microwatt handles MTSPR, MFSPR, DCBZ and TLBIE.
-    # libre-soc has own SPR unit
-    # libre-soc MMU supports MTSPR and MFSPR but **ONLY** for the subset
-    # of SPRs it actually does.
-    # other instructions here -> must be load/store
-
-    def case_mmu_ldst(self):
-        lst = [
-                #"mtspr 720, 1", # XXX do not execute unsupported instructions
-                "lhz 3, 0(1)"      # load some data
-              ]
-
-        initial_regs = [0] * 32
-        
-        # set process table
-        prtbl = 0x1000000
-        initial_regs[1] = prtbl
-        
-        initial_sprs = {'DSISR': 0, 'DAR': 0,
-                         720: 0}
-        self.add_case(Program(lst, bigendian),
-                      initial_regs, initial_sprs)
-
-
-
-
-if __name__ == "__main__":
-    unittest.main(exit=False)
-    suite = unittest.TestSuite()
-    suite.addTest(TestRunner(MMUTestCase().test_data, microwatt_mmu=True,
-                             rom=default_mem))
-    runner = unittest.TextTestRunner()
-    runner.run(suite)
-
-#  soc/simple/test/test_runner.py

diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py
index eacbd44784a7247cf48ea839b8860e5d66f85448..446dd22703895dab5914fb9ee0c95f7b8f37c3f9 100644 (file)
--- a/src/soc/fu/mmu/test/test_pipe_caller.py
+++ b/src/soc/fu/mmu/test/test_pipe_caller.py
@@ -6,19 +6,17 @@ from nmutil.sim_tmp_alternative import Simulator, Settle
 
 from nmigen.cli import rtlil
 import unittest
-from openpower.decoder.isa.caller import ISACaller, special_sprs
-from openpower.decoder.power_decoder import (create_pdecode)
-from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_decoder import create_pdecode
+from openpower.decoder.power_decoder2 import PowerDecode2
 from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
-from openpower.decoder.selectable_int import SelectableInt
 from openpower.simulator.program import Program
 from openpower.decoder.isa.all import ISA
 from openpower.endian import bigendian
 from openpower.consts import MSR
 
+from openpower.test.mmu.mmu_cases import MMUTestCase
 
-from openpower.test.common import (
-    TestAccumulatorBase, skip_case, TestCase, ALUHelpers)
+from openpower.test.common import (TestAccumulatorBase, skip_case, ALUHelpers)
 #from soc.fu.spr.pipeline import SPRBasePipe
 #from soc.fu.spr.pipe_data import SPRPipeSpec
 from soc.fu.mmu.fsm import FSMMMUStage
@@ -26,7 +24,7 @@ from soc.fu.mmu.pipe_data import MMUPipeSpec
 import random
 
 from soc.fu.div.test.helper import (log_rand, get_cu_inputs,
-                                    set_alu_inputs, DivTestHelper)
+                                    set_alu_inputs)
 
 import power_instruction_analyzer as pia
 
@@ -69,31 +67,14 @@ def check_fsm_outputs(fsm, pdecode2, sim, code):
     return None #TODO
 
 #incomplete test - connect fsm inputs first
-class MMUTestCase(TestAccumulatorBase):
-    # MMU handles MTSPR, MFSPR, DCBZ and TLBIE.
-    # other instructions here -> must be load/store
-
-    #before running the test case: set DISR and DAR
-
-    def case_mfspr_after_invalid_load(self):
-        lst = [ # TODO -- set SPR on both sinulator and port interface
-                "mfspr 1, 18", # DSISR to reg 1
-                "mfspr 2, 19", # DAR to reg 2
-                # TODO -- verify returned sprvals
-              ]
-
-        initial_regs = [0] * 32
-
-        initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
-        self.add_case(Program(lst, bigendian),
-                      initial_regs, initial_sprs)
-
+class MMUIlangCase(TestAccumulatorBase):
     #def case_ilang(self):
     #    pspec = SPRPipeSpec(id_wid=2)
     #    alu = SPRBasePipe(pspec)
     #    vl = rtlil.convert(alu, ports=alu.ports())
     #    with open("trap_pipeline.il", "w") as f:
     #        f.write(vl)
+    pass
 
 
 class TestRunner(unittest.TestCase):
@@ -256,6 +237,7 @@ if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
     suite.addTest(TestRunner(MMUTestCase().test_data))
+    suite.addTest(TestRunner(MMUIlangCase().test_data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)