uMaxThreads = 192;
uMaxStackEntries = 256;
break;
+ case CHIP_FAMILY_BARTS:
+ uSqNumCfInsts = 2;
+ bVC_ENABLE = GL_TRUE;
+ uMaxGPRs = 256;
+ uPSThreadCount = 128;
+ uMaxThreads = 248;
+ uMaxStackEntries = 512;
+ break;
+ case CHIP_FAMILY_TURKS:
+ uSqNumCfInsts = 2;
+ bVC_ENABLE = GL_TRUE;
+ uMaxGPRs = 256;
+ uPSThreadCount = 128;
+ uMaxThreads = 248;
+ uMaxStackEntries = 256;
+ break;
+ case CHIP_FAMILY_CAICOS:
+ uSqNumCfInsts = 1;
+ bVC_ENABLE = GL_FALSE;
+ uMaxGPRs = 256;
+ uPSThreadCount = 128;
+ uMaxThreads = 192;
+ uMaxStackEntries = 256;
+ break;
default:
uSqNumCfInsts = 2;
bVC_ENABLE = GL_TRUE;
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
if( (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_CEDAR)
- &&(context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_PALM) )
+ &&(context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_CAICOS) )
{
r700->bShaderUseMemConstant = GL_TRUE;
}
#define PCI_CHIP_PALM_9804 0x9804
#define PCI_CHIP_PALM_9805 0x9805
+#define PCI_CHIP_BARTS_6720 0x6720
+#define PCI_CHIP_BARTS_6721 0x6721
+#define PCI_CHIP_BARTS_6722 0x6722
+#define PCI_CHIP_BARTS_6723 0x6723
+#define PCI_CHIP_BARTS_6724 0x6724
+#define PCI_CHIP_BARTS_6725 0x6725
+#define PCI_CHIP_BARTS_6726 0x6726
+#define PCI_CHIP_BARTS_6727 0x6727
+#define PCI_CHIP_BARTS_6728 0x6728
+#define PCI_CHIP_BARTS_6729 0x6729
+#define PCI_CHIP_BARTS_6738 0x6738
+#define PCI_CHIP_BARTS_6739 0x6739
+
+#define PCI_CHIP_TURKS_6740 0x6740
+#define PCI_CHIP_TURKS_6741 0x6741
+#define PCI_CHIP_TURKS_6742 0x6742
+#define PCI_CHIP_TURKS_6743 0x6743
+#define PCI_CHIP_TURKS_6744 0x6744
+#define PCI_CHIP_TURKS_6745 0x6745
+#define PCI_CHIP_TURKS_6746 0x6746
+#define PCI_CHIP_TURKS_6747 0x6747
+#define PCI_CHIP_TURKS_6748 0x6748
+#define PCI_CHIP_TURKS_6749 0x6749
+#define PCI_CHIP_TURKS_6750 0x6750
+#define PCI_CHIP_TURKS_6758 0x6758
+#define PCI_CHIP_TURKS_6759 0x6759
+
+#define PCI_CHIP_CAICOS_6760 0x6760
+#define PCI_CHIP_CAICOS_6761 0x6761
+#define PCI_CHIP_CAICOS_6762 0x6762
+#define PCI_CHIP_CAICOS_6763 0x6763
+#define PCI_CHIP_CAICOS_6764 0x6764
+#define PCI_CHIP_CAICOS_6765 0x6765
+#define PCI_CHIP_CAICOS_6766 0x6766
+#define PCI_CHIP_CAICOS_6767 0x6767
+#define PCI_CHIP_CAICOS_6768 0x6768
+#define PCI_CHIP_CAICOS_6770 0x6770
+#define PCI_CHIP_CAICOS_6779 0x6779
+
enum {
CHIP_FAMILY_R100,
CHIP_FAMILY_RV100,
CHIP_FAMILY_CYPRESS,
CHIP_FAMILY_HEMLOCK,
CHIP_FAMILY_PALM,
+ CHIP_FAMILY_BARTS,
+ CHIP_FAMILY_TURKS,
+ CHIP_FAMILY_CAICOS,
CHIP_FAMILY_LAST
};
case CHIP_FAMILY_CYPRESS: return "CYPRESS";
case CHIP_FAMILY_HEMLOCK: return "HEMLOCK";
case CHIP_FAMILY_PALM: return "PALM";
+ case CHIP_FAMILY_BARTS: return "BARTS";
+ case CHIP_FAMILY_TURKS: return "TURKS";
+ case CHIP_FAMILY_CAICOS: return "CAICOS";
default: return "unknown";
}
}
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
+ case PCI_CHIP_BARTS_6720:
+ case PCI_CHIP_BARTS_6721:
+ case PCI_CHIP_BARTS_6722:
+ case PCI_CHIP_BARTS_6723:
+ case PCI_CHIP_BARTS_6724:
+ case PCI_CHIP_BARTS_6725:
+ case PCI_CHIP_BARTS_6726:
+ case PCI_CHIP_BARTS_6727:
+ case PCI_CHIP_BARTS_6728:
+ case PCI_CHIP_BARTS_6729:
+ case PCI_CHIP_BARTS_6738:
+ case PCI_CHIP_BARTS_6739:
+ screen->chip_family = CHIP_FAMILY_BARTS;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_TURKS_6740:
+ case PCI_CHIP_TURKS_6741:
+ case PCI_CHIP_TURKS_6742:
+ case PCI_CHIP_TURKS_6743:
+ case PCI_CHIP_TURKS_6744:
+ case PCI_CHIP_TURKS_6745:
+ case PCI_CHIP_TURKS_6746:
+ case PCI_CHIP_TURKS_6747:
+ case PCI_CHIP_TURKS_6748:
+ case PCI_CHIP_TURKS_6749:
+ case PCI_CHIP_TURKS_6750:
+ case PCI_CHIP_TURKS_6758:
+ case PCI_CHIP_TURKS_6759:
+ screen->chip_family = CHIP_FAMILY_TURKS;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_CAICOS_6760:
+ case PCI_CHIP_CAICOS_6761:
+ case PCI_CHIP_CAICOS_6762:
+ case PCI_CHIP_CAICOS_6763:
+ case PCI_CHIP_CAICOS_6764:
+ case PCI_CHIP_CAICOS_6765:
+ case PCI_CHIP_CAICOS_6766:
+ case PCI_CHIP_CAICOS_6767:
+ case PCI_CHIP_CAICOS_6768:
+ case PCI_CHIP_CAICOS_6770:
+ case PCI_CHIP_CAICOS_6779:
+ screen->chip_family = CHIP_FAMILY_CAICOS;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
default:
fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
device_id);