rename to fabric

diff --git a/src/jsoncreate.py b/src/jsoncreate.py
index ea445e84621ea04fea1d83f235e34efa0677adf9..3ace57b04498a5bc0147e4d4a44883a6b5edb6d7 100644 (file)
--- a/src/jsoncreate.py
+++ b/src/jsoncreate.py
@@ -2,12 +2,12 @@ from parse import Parse
 from pprint import pprint
 import json
 
-# map pins to litex name conventions, primarily for use in coriolis2
+# map pins to fabric name conventions, primarily for use in coriolis2
 # yes this is a mess.  it'll do the job though.  improvements later
 def pinparse(psp, pinspec):
     p = Parse(pinspec, verify=False)
     pinmap = {}
-    litexmap = {}
+    fabricmap = {}
 
     print ("muxed cells", p.muxed_cells)
     print ("muxed cell banks", p.muxed_cells_bank)
@@ -29,7 +29,7 @@ def pinparse(psp, pinspec):
         name = clist[1]
         x = clist[2]
         orig_name = name
-        litex_name = None
+        fabric_name = None
         domain = None # TODO, get this from the PinSpec.  sigh
         padnum = int(padnum)
         start = p.bankstart[bank]
@@ -97,7 +97,7 @@ def pinparse(psp, pinspec):
                 prefix = 'spimaster_'
             else:
                 prefix = 'spisdcard_'
-            litex_name = name[:6] + suffix
+            fabric_name = name[:6] + suffix
             name = prefix + suffix
             pad = ['p_' + name, name, name]
         # SD/MMC
@@ -115,7 +115,7 @@ def pinparse(psp, pinspec):
             else:
                 name = 'sdcard_' + name[4:]
                 pad = ['p_' + name, name, name]
-            litex_name = orig_name[:4] + "_".join(name.split("_")[1:])
+            fabric_name = orig_name[:4] + "_".join(name.split("_")[1:])
         # SDRAM
         elif name.startswith('sdr'):
             domain = 'SDR'
@@ -151,7 +151,7 @@ def pinparse(psp, pinspec):
             else:
                 name = 'sdram_' + name[4:]
                 pad = ['p_' + name, name, name]
-            litex_name = orig_name[:4] + "_".join(name.split("_")[1:])
+            fabric_name = orig_name[:4] + "_".join(name.split("_")[1:])
         # UART
         elif name.startswith('uart'):
             domain = 'UART'
@@ -166,12 +166,12 @@ def pinparse(psp, pinspec):
             name2 = 'gpio_%%s(%s)' % i
             pad = ['p_' + name, name, name2 % 'o', name2 % 'i', name2 % 'oe']
             print ("GPIO pad", name, pad)
-            litex_name = "gpio_%s" % gbank + "_".join(name.split("_")[1:])
+            fabric_name = "gpio_%s" % gbank + "_".join(name.split("_")[1:])
         # I2C master-only
         elif name.startswith('mtwi'):
             domain = 'MTWI'
             suffix = name[4:]
-            litex_name = 'mtwi' + suffix
+            fabric_name = 'mtwi' + suffix
             name = 'i2c' + suffix
             if name.startswith('i2c_sda'):
                 name2 = 'i2c_sda_%s'
@@ -204,8 +204,8 @@ def pinparse(psp, pinspec):
             pad = ['p_' + name, name, name]
             print ("GPIO pad", name, pad)
 
-        if litex_name is None:
-            litex_name = name
+        if fabric_name is None:
+            fabric_name = name
 
         # JTAG domain
         if name and name.startswith('jtag'):
@@ -229,7 +229,7 @@ def pinparse(psp, pinspec):
                         clocks[domain] = name
             # record remap
             pinmap[orig_name] = name
-            litexmap[litex_name] = name
+            fabricmap[fabric_name] = name
 
         # add pad to iopads
         if domain and pad is not None:
@@ -297,7 +297,7 @@ def pinparse(psp, pinspec):
               'pads.instances' : iopads,
               'pins.specs' : psp.byspec,
               'pins.map' : pinmap,
-              'litex.map' : litexmap,
+              'fabric.map' : fabricmap,
               'chip.domains' : domains,
               'chip.clocks' : clocks,
               'chip.n_intpower': n_intpower,

diff --git a/src/pinmux_generator.py b/src/pinmux_generator.py
index 074f4aaee8b8fd773697458e560e6d7c758d82c1..960509e670e445bfc3257880b77663342f768ade 100644 (file)
--- a/src/pinmux_generator.py
+++ b/src/pinmux_generator.py
@@ -91,7 +91,7 @@ if __name__ == '__main__':
             with open(pyname, "w") as pyf:
                 ps = module.pinspec()
                 pinout, bankspec, pin_spec, fixedpins = ps.write(of)
-                #chip['litex.map'] = litexmap
+                #chip['fabric.map'] = fabricmap
                 if testing:
                     dummytest(ps, output_dir, output_type)
                 else:
@@ -99,9 +99,9 @@ if __name__ == '__main__':
                             bankspec, ps.muxwidths, pin_spec, fixedpins,
                             ps.fastbus)
                 pm, chip = jsoncreate.pinparse(ps, pinspec)
-                litexmap = ps.pywrite(pyf, pm)
+                fabricmap = ps.pywrite(pyf, pm)
                 jchip = json.dumps(chip)
-                with open("%s/litex_pinpads.json" % pinspec, "w") as f:
+                with open("%s/fabric_pinpads.json" % pinspec, "w") as f:
                     f.write(jchip)
                 # octavius: please keep line-lengths to below 80 chars
                 # TODO: fix create_sv to allow different packages

diff --git a/src/spec/ifaceprint.py b/src/spec/ifaceprint.py
index 51f622a8aaf24c9ad1d40cf9ebf5d3ee78a7e761..944ec180e8e62d843c75b9584c6e52dd53447470 100644 (file)
--- a/src/spec/ifaceprint.py
+++ b/src/spec/ifaceprint.py
@@ -840,12 +840,12 @@ def python_dict_fns(of, pinmap, pins, function_names):
     print (pinmap)
 
     pd = python_pindict(of, {}, pins, function_names, 'pindict', False)
-    ld = python_pindict(of, pinmap, pins, function_names, 'litexdict', True)
+    ld = python_pindict(of, pinmap, pins, function_names, 'fabricdict', True)
 
     print ("pd", pd)
     print ("ld", ld)
     # process results and create name map
-    litexmap = OrderedDict()
+    fabricmap = OrderedDict()
     for k in pd.keys():
         pl = pd[k]
         ll = ld[k]
@@ -854,13 +854,13 @@ def python_dict_fns(of, pinmap, pins, function_names):
             lname = lname[:-1] # strip direction +/-/*
             if k in ['eint', 'pwm', 'gpio', 'vdd', 'vss']: # sigh
                 lname = "%s_%s" % (k, lname)
-            litexmap[pname] = lname
-    print ("litexmap", litexmap)
-    of.write("litexmap = {\n")
-    for k, v in litexmap.items():
+            fabricmap[pname] = lname
+    print ("fabricmap", fabricmap)
+    of.write("fabricmap = {\n")
+    for k, v in fabricmap.items():
         of.write("\t'%s': '%s',\n" % (k, v))
     of.write("}\n")
-    return litexmap
+    return fabricmap
 
 
 def display_fns(of, bankspec, pins, function_names):

diff --git a/src/spec/ls180.py b/src/spec/ls180.py
index 2454b392cf1dcacad879b5bbd6869e945c92a327..308bd67b120bab2b0e4e24ff30ee2a10eead175f 100644 (file)
--- a/src/spec/ls180.py
+++ b/src/spec/ls180.py
@@ -104,9 +104,9 @@ def pinspec():
     ps.vdd("E", ('N', 7), 0, 6, 1)
     ps.vdd("I", ('N', 8), 0, 6, 1)
     ps.vss("I", ('N', 9), 0, 6, 1)
-    #ps.pwm("", ('N', 2), 0, 0, 2)  comment out (litex problem 25mar2021)
-    #ps.mspi("1", ('N', 7), 0)       comment out (litex problem 25mar2021)
-    #ps.sdmmc("0", ('N', 11), 0)     # comment out (litex problem 25mar2021)
+    #ps.pwm("", ('N', 2), 0, 0, 2)  comment out (fabric problem 25mar2021)
+    #ps.mspi("1", ('N', 7), 0)       comment out (fabric problem 25mar2021)
+    #ps.sdmmc("0", ('N', 11), 0)     # comment out (fabric problem 25mar2021)
     ps.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
     ps.vss("I", ('N', 22), 0, 7, 1)
     ps.vdd("I", ('N', 23), 0, 7, 1)
@@ -125,11 +125,11 @@ def pinspec():
     # lists (interfaces, EINTs, PWMs) from available pins.
 
     ls180 = [
-            # 'SD0', litex problem 25mar2021
+            # 'SD0', fabric problem 25mar2021
             'UART0', 'GPIOS', 'GPIOE', 'JTAG', 'PWM', 'EINT',
              'VDD', 'VSS', 'SYS',
                 'MTWI', 'MSPI0',
-                # 'MSPI1', litex problem 25mar2021
+                # 'MSPI1', fabric problem 25mar2021
                 'SDR']
     ls180_eint = []
     ls180_pwm = []#['B0:PWM_0']

diff --git a/src/spec/ngi_router.py b/src/spec/ngi_router.py
index a3bf47177965ec47f373d68a90f7919eca858ced..d20d045f71b4e9e5d56c9aaf33bae1a06f87627f 100644 (file)
--- a/src/spec/ngi_router.py
+++ b/src/spec/ngi_router.py
@@ -117,9 +117,6 @@ def pinspec():
     ps.vss("I", ('N', 9), 0, 6, 1)
     ps.gpio("", ('N', 10), 0, 6, 12) # GPIO 4-17
     ps.rgmii("0", ('N', 10), 1, 6, 12) # more RGMII-1
-    #ps.pwm("", ('N', 2), 0, 0, 2)  comment out (litex problem 25mar2021)
-    #ps.mspi("1", ('N', 7), 0)       comment out (litex problem 25mar2021)
-    #ps.sdmmc("0", ('N', 11), 0)     # comment out (litex problem 25mar2021)
     ps.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
     ps.vss("I", ('N', 23), 0, 7, 1)
     ps.vdd("I", ('N', 24), 0, 7, 1)
@@ -138,12 +135,10 @@ def pinspec():
     # lists (interfaces, EINTs, PWMs) from available pins.
 
     ls180 = [
-            # 'SD0', litex problem 25mar2021
             'UART0', 'JTAG', 'PWM', 'EINT',
              'VDD', 'VSS', 'SYS',
                 'MTWI', 'MSPI0',
                 'RG0', 'RG1',
-                # 'MSPI1', litex problem 25mar2021
                 'SDR']
     ls180_eint = []
     ls180_pwm = []#['B0:PWM_0']