misc: Remove any reference to the ALPHA ISA

Change-Id: Ie761cd69ae0e8e632ca2b92e63a404e8804f0e6f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30015
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 436e661bdee354349f2782e606b4b0f8540609ce..9a4d7fc51185f4abbd9355d07140b2c937962202 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -102,7 +102,6 @@ sim-power: Power modeling
 stats: Updates to statistics for regressions
 
 system: System boot code and related components
-system-alpha:
 system-arm:
   Andreas Sandberg <andreas.sandberg@arm.com>
   Giacomo Travaglini <giacomo.travaglini@arm.com>

diff --git a/SConstruct b/SConstruct
index 370cd60241f18dbb0deac707fb8b57ecc91fcb9b..3a03af4974dea77b59392a8e9f2ecea5c9364874 100755 (executable)
--- a/SConstruct
+++ b/SConstruct
@@ -988,7 +988,7 @@ all_isa_list.sort()
 all_gpu_isa_list.sort()
 
 sticky_vars.AddVariables(
-    EnumVariable('TARGET_ISA', 'Target ISA', 'alpha', all_isa_list),
+    EnumVariable('TARGET_ISA', 'Target ISA', 'null', all_isa_list),
     EnumVariable('TARGET_GPU_ISA', 'Target GPU ISA', 'hsail', all_gpu_isa_list),
     ListVariable('CPU_MODELS', 'CPU models',
                  sorted(n for n,m in CpuModel.dict.items() if m.default),

diff --git a/src/arch/mips/idle_event.hh b/src/arch/mips/idle_event.hh
index 14019189a7880b30fb32b75fcdf1f706aed3f438..d332b872a979ac355ea8c2777cc69808efb33902 100644 (file)
--- a/src/arch/mips/idle_event.hh
+++ b/src/arch/mips/idle_event.hh
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __KERN_MIPS_IDLE_EVENT_HH__
-#define __KERN_MIPS_IDLE_EVENT_HH__
+#ifndef __ARCH_MIPS_IDLE_EVENT_HH__
+#define __ARCH_MIPS_IDLE_EVENT_HH__
 
 #include "cpu/pc_event.hh"
 
@@ -40,4 +40,4 @@ class IdleStartEvent : public PCEvent
     virtual void process(ThreadContext *tc);
 };
 
-#endif // __KERN_ALPHA_IDLE_EVENT_HH__
+#endif // __ARCH_MIPS_IDLE_EVENT_HH__

diff --git a/src/arch/sparc/kernel_stats.hh b/src/arch/sparc/kernel_stats.hh
index 80b8a04a6ee2d0e57953656e1b9d612cb5bce418..41a8dd04d787cb69ccb5c55bb02d0fc66396945d 100644 (file)
--- a/src/arch/sparc/kernel_stats.hh
+++ b/src/arch/sparc/kernel_stats.hh
@@ -46,7 +46,7 @@ class Statistics : public ::Kernel::Statistics
     {}
 };
 
-} // namespace AlphaISA::Kernel
-} // namespace AlphaISA
+} // namespace SparcISA::Kernel
+} // namespace SparcISA
 
 #endif // __ARCH_SPARC_KERNEL_STATS_HH__

diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore
index b8cfc7f50815640f94881392c57ff70da5c5b9d2..c76d7c685dbdfdc28c3e4eb24a012e0df395c2a4 100644 (file)
--- a/tests/gem5/.testignore
+++ b/tests/gem5/.testignore
@@ -93,95 +93,59 @@ test-insttest-rv64i-linux-DerivO3CPU-RISCV-i386-fast
 test-insttest-linux-AtomicSimpleCPU-SPARC-i386-fast
 test-insttest-linux-TimingSimpleCPU-SPARC-i386-fast
 test-hello-linux-MinorCPU-RISCV-x86_64-debug
-test-hello-linux-MinorCPU-ALPHA-x86_64-debug
 test-hello-linux-TimingSimpleCPU-SPARC-x86_64-debug
 test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-debug
 test-hello-linux-TimingSimpleCPU-MIPS-x86_64-debug
 test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-debug
 test-hello-linux-DerivO3CPU-MIPS-x86_64-debug
-test-hello-linux-TimingSimpleCPU-ALPHA-x86_64-debug
-test-hello-linux-AtomicSimpleCPU-ALPHA-x86_64-debug
-test-hello-linux-DerivO3CPU-ALPHA-x86_64-debug
 test-hello-linux-MinorCPU-RISCV-x86_64-fast
-test-hello-linux-MinorCPU-ALPHA-x86_64-fast
 test-hello-linux-TimingSimpleCPU-SPARC-x86_64-fast
 test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-fast
 test-hello-linux-TimingSimpleCPU-MIPS-x86_64-fast
 test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-fast
 test-hello-linux-DerivO3CPU-MIPS-x86_64-fast
-test-hello-linux-TimingSimpleCPU-ALPHA-x86_64-fast
-test-hello-linux-AtomicSimpleCPU-ALPHA-x86_64-fast
-test-hello-linux-DerivO3CPU-ALPHA-x86_64-fast
 test-hello-linux-MinorCPU-RISCV-x86_64-opt
-test-hello-linux-MinorCPU-ALPHA-x86_64-opt
 test-hello-linux-TimingSimpleCPU-SPARC-x86_64-opt
 test-hello-linux-AtomicSimpleCPU-SPARC-x86_64-opt
 test-hello-linux-TimingSimpleCPU-MIPS-x86_64-opt
 test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-opt
 test-hello-linux-DerivO3CPU-MIPS-x86_64-opt
-test-hello-linux-TimingSimpleCPU-ALPHA-x86_64-opt
-test-hello-linux-AtomicSimpleCPU-ALPHA-x86_64-opt
-test-hello-linux-DerivO3CPU-ALPHA-x86_64-opt
 test-hello-linux-MinorCPU-RISCV-arch64-debug
-test-hello-linux-MinorCPU-ALPHA-arch64-debug
 test-hello-linux-TimingSimpleCPU-SPARC-arch64-debug
 test-hello-linux-AtomicSimpleCPU-SPARC-arch64-debug
 test-hello-linux-TimingSimpleCPU-MIPS-arch64-debug
 test-hello-linux-AtomicSimpleCPU-MIPS-arch64-debug
 test-hello-linux-DerivO3CPU-MIPS-arch64-debug
-test-hello-linux-TimingSimpleCPU-ALPHA-arch64-debug
-test-hello-linux-AtomicSimpleCPU-ALPHA-arch64-debug
-test-hello-linux-DerivO3CPU-ALPHA-arch64-debug
 test-hello-linux-MinorCPU-RISCV-arch64-fast
-test-hello-linux-MinorCPU-ALPHA-arch64-fast
 test-hello-linux-TimingSimpleCPU-SPARC-arch64-fast
 test-hello-linux-AtomicSimpleCPU-SPARC-arch64-fast
 test-hello-linux-TimingSimpleCPU-MIPS-arch64-fast
 test-hello-linux-AtomicSimpleCPU-MIPS-arch64-fast
 test-hello-linux-DerivO3CPU-MIPS-arch64-fast
-test-hello-linux-TimingSimpleCPU-ALPHA-arch64-fast
-test-hello-linux-AtomicSimpleCPU-ALPHA-arch64-fast
-test-hello-linux-DerivO3CPU-ALPHA-arch64-fast
 test-hello-linux-MinorCPU-RISCV-arch64-opt
-test-hello-linux-MinorCPU-ALPHA-arch64-opt
 test-hello-linux-TimingSimpleCPU-SPARC-arch64-opt
 test-hello-linux-AtomicSimpleCPU-SPARC-arch64-opt
 test-hello-linux-TimingSimpleCPU-MIPS-arch64-opt
 test-hello-linux-AtomicSimpleCPU-MIPS-arch64-opt
 test-hello-linux-DerivO3CPU-MIPS-arch64-opt
-test-hello-linux-TimingSimpleCPU-ALPHA-arch64-opt
-test-hello-linux-AtomicSimpleCPU-ALPHA-arch64-opt
-test-hello-linux-DerivO3CPU-ALPHA-arch64-opt
 test-hello-linux-MinorCPU-RISCV-i386-debug
-test-hello-linux-MinorCPU-ALPHA-i386-debug
 test-hello-linux-TimingSimpleCPU-SPARC-i386-debug
 test-hello-linux-AtomicSimpleCPU-SPARC-i386-debug
 test-hello-linux-TimingSimpleCPU-MIPS-i386-debug
 test-hello-linux-AtomicSimpleCPU-MIPS-i386-debug
 test-hello-linux-DerivO3CPU-MIPS-i386-debug
-test-hello-linux-TimingSimpleCPU-ALPHA-i386-debug
-test-hello-linux-AtomicSimpleCPU-ALPHA-i386-debug
-test-hello-linux-DerivO3CPU-ALPHA-i386-debug
 test-hello-linux-MinorCPU-RISCV-i386-fast
-test-hello-linux-MinorCPU-ALPHA-i386-fast
 test-hello-linux-TimingSimpleCPU-SPARC-i386-fast
 test-hello-linux-AtomicSimpleCPU-SPARC-i386-fast
 test-hello-linux-TimingSimpleCPU-MIPS-i386-fast
 test-hello-linux-AtomicSimpleCPU-MIPS-i386-fast
 test-hello-linux-DerivO3CPU-MIPS-i386-fast
-test-hello-linux-TimingSimpleCPU-ALPHA-i386-fast
-test-hello-linux-AtomicSimpleCPU-ALPHA-i386-fast
-test-hello-linux-DerivO3CPU-ALPHA-i386-fast
 test-hello-linux-MinorCPU-RISCV-i386-opt
-test-hello-linux-MinorCPU-ALPHA-i386-opt
 test-hello-linux-TimingSimpleCPU-SPARC-i386-opt
 test-hello-linux-AtomicSimpleCPU-SPARC-i386-opt
 test-hello-linux-TimingSimpleCPU-MIPS-i386-opt
 test-hello-linux-AtomicSimpleCPU-MIPS-i386-opt
 test-hello-linux-DerivO3CPU-MIPS-i386-opt
-test-hello-linux-TimingSimpleCPU-ALPHA-i386-opt
-test-hello-linux-AtomicSimpleCPU-ALPHA-i386-opt
-test-hello-linux-DerivO3CPU-ALPHA-i386-opt
 test-atomic-DerivO3CPU-SPARC-x86_64-opt
 test-atomic-TimingSimpleCPU-SPARC-x86_64-opt
 test-atomic-DerivO3CPU-SPARC-x86_64-debug

diff --git a/tests/gem5/hello_se/test_hello_se.py b/tests/gem5/hello_se/test_hello_se.py
index 260daad51122d1492615c09265cf3e618d519437..96f6d33a326095dc3210799c6ac83a8af937d6a9 100644 (file)
--- a/tests/gem5/hello_se/test_hello_se.py
+++ b/tests/gem5/hello_se/test_hello_se.py
@@ -47,7 +47,6 @@ from testlib import *
 static_progs = {
     'x86': ('hello64-static', 'hello32-static'),
     'arm': ('hello64-static', 'hello32-static'),
-    'alpha': ('hello',),
     'mips': ('hello',),
     'riscv': ('hello',),
     'sparc': ('hello',)
@@ -60,7 +59,6 @@ dynamic_progs = {
 cpu_types = {
     'x86': ('TimingSimpleCPU', 'AtomicSimpleCPU', 'DerivO3CPU'),
     'arm' :  ('TimingSimpleCPU', 'AtomicSimpleCPU','DerivO3CPU'),
-    'alpha': ('TimingSimpleCPU', 'AtomicSimpleCPU', 'DerivO3CPU', 'MinorCPU'),
     'mips' : ('TimingSimpleCPU', 'AtomicSimpleCPU', 'DerivO3CPU'),
     'riscv' : ('TimingSimpleCPU', 'AtomicSimpleCPU', 'DerivO3CPU', 'MinorCPU'),
     'sparc' : ('TimingSimpleCPU', 'AtomicSimpleCPU')
@@ -69,7 +67,6 @@ cpu_types = {
 supported_os = {
     'x86': ('linux',),
     'arm' : ('linux',),
-    'alpha' : ('linux',),
     'mips' : ('linux',),
     'riscv' : ('linux',),
     'sparc' : ('linux',)

diff --git a/tests/testing/tests.py b/tests/testing/tests.py
index 042180d796b0bfa20accf2381ad15b194ffabb74..26f431c8d4a27fdc889213568e32e0b7fc5e7a43 100755 (executable)
--- a/tests/testing/tests.py
+++ b/tests/testing/tests.py
@@ -81,17 +81,6 @@ ClassicConfig = namedtuple("ClassicConfig", (
 # original name. See get_tests() for details.
 #
 arch_configs = {
-    ("alpha", None) : (
-        'tsunami-simple-atomic',
-        'tsunami-simple-timing',
-        'tsunami-simple-atomic-dual',
-        'tsunami-simple-timing-dual',
-        'twosys-tsunami-simple-atomic',
-        'tsunami-o3', 'tsunami-o3-dual',
-        'tsunami-minor', 'tsunami-minor-dual',
-        'tsunami-switcheroo-full',
-    ),
-
     ("arm", None) : (
         'simple-atomic-dummychecker',
         'o3-timing-checker',

diff --git a/util/checkpoint-tester.py b/util/checkpoint-tester.py
index e7bd45e24a6cc8654a930e185c83afe6700b1512..5ad9219be7f163da39820bf0abead491de259278 100755 (executable)
--- a/util/checkpoint-tester.py
+++ b/util/checkpoint-tester.py
@@ -55,11 +55,11 @@
 #
 # Examples:
 #
-# util/checkpoint-tester.py -i 400000 -- build/ALPHA_SE/m5.opt \
-#      configs/example/se.py -c tests/test-progs/hello/bin/alpha/tru64/hello \
+# util/checkpoint-tester.py -i 400000 -- build/<ISA>/m5.opt \
+#      configs/example/se.py -c tests/test-progs/hello/bin/<isa>/tru64/hello \
 #      --output=progout --errout=progerr
 #
-# util/checkpoint-tester.py -i 200000000000 -- build/ALPHA_FS/m5.opt \
+# util/checkpoint-tester.py -i 200000000000 -- build/<ISA>/m5.opt \
 #      configs/example/fs.py --script tests/halt.sh
 #
 

diff --git a/util/compile b/util/compile
index 1ef3f2cca19d46e39ff10c68b45a2eb15df62a1c..ce2b4188e9e162ad64c9f0e95540b759378b5c19 100755 (executable)
--- a/util/compile
+++ b/util/compile
@@ -155,7 +155,6 @@ add_option('-a', "--all-bin", default=False, action='store_true',
            help="compile debug, opt, and fast binaries")
 
 set_group("ISA options")
-bool_option("alpha", default=False, help="compile Alpha")
 bool_option("mips", default=False, help="compile MIPS")
 bool_option("sparc", default=False, help="compile SPARC")
 add_option('-i', "--all-isa", default=False, action='store_true',
@@ -198,21 +197,15 @@ if not binaries:
     binaries.append('m5.debug')
 
 if options.all_isa:
-    options.alpha = True
     options.mips = True
     options.sparc = True
 
 isas = []
-if options.alpha:
-    isas.append('alpha')
 if options.mips:
     isas.append('mips')
 if options.sparc:
     isas.append('sparc')
 
-if not isas:
-    isas.append('alpha')
-
 modes = []
 if options.syscall:
     modes.append('syscall')
@@ -227,10 +220,9 @@ if not modes:
 #
 
 # valid combinations of ISA and emulation mode
-valid = { ('alpha', 'syscall') : 'ALPHA_SE',
-          ('alpha', 'fullsys') : 'ALPHA_FS',
-          ('mips',  'syscall') : 'MIPS_SE',
-          ('sparc', 'syscall') : 'SPARC_SE' }
+valid = {
+    ('mips',  'syscall') : 'MIPS_SE',
+    ('sparc', 'syscall') : 'SPARC_SE' }
 
 # experimental combinations of ISA and emulation mode
 experiment = { ('mips', 'fullsys') : 'MIPS_FS',

diff --git a/util/cpt_upgraders/isa-is-simobject.py b/util/cpt_upgraders/isa-is-simobject.py
index 8633bf0ed44b6a623ca2b24fa7a974799d53df4e..72c62568acb4ab7a130dd1df445a0fabe15026f2 100644 (file)
--- a/util/cpt_upgraders/isa-is-simobject.py
+++ b/util/cpt_upgraders/isa-is-simobject.py
@@ -3,7 +3,6 @@
 def upgrader(cpt):
     isa = cpt.get('root','isa')
     isa_fields = {
-        "alpha" : ( "fpcr", "uniq", "lock_flag", "lock_addr", "ipr" ),
         "arm" : ( "miscRegs" ),
         "sparc" : ( "asi", "tick", "fprs", "gsr", "softint", "tick_cmpr",
                     "stick", "stick_cmpr", "tpc", "tnpc", "tstate", "tt",

diff --git a/util/git-commit-msg.py b/util/git-commit-msg.py
index 92e8100be3f79c451d5830738c2d767108d7cec3..500c5c71d5000d3884df7609ad23bdeb83abb564 100755 (executable)
--- a/util/git-commit-msg.py
+++ b/util/git-commit-msg.py
@@ -88,13 +88,13 @@ def _validateTags(commit_header):
     # @todo this is error prone, and should be extracted automatically from
     #       a file
 
-    valid_tags = ["arch", "arch-alpha", "arch-arm", "arch-gcn3", "arch-hsail",
+    valid_tags = ["arch", "arch-arm", "arch-gcn3", "arch-hsail",
         "arch-mips", "arch-power", "arch-riscv", "arch-sparc", "arch-x86",
         "base", "configs", "cpu", "cpu-kvm", "cpu-minor", "cpu-o3",
         "cpu-simple", "dev", "dev-arm", "dev-virtio", "ext", "fastmodel",
         "gpu-compute", "learning-gem5", "mem", "mem-cache", "mem-garnet",
         "mem-ruby", "misc", "python", "scons", "sim", "sim-se", "sim-power",
-        "stats", "system", "system-alpha", "system-arm", "systemc", "tests",
+        "stats", "system", "system-arm", "systemc", "tests",
         "util", "RFC", "WIP"]
 
     tags = ''.join(commit_header.split(':')[0].split()).split(',')